The present invention is related to the fabrication method for a thin film semiconductor device, the thin film semiconductor device itself, liquid crystal displays, and electronic devices applicable to active matrix liquid crystal displays and the like.
In recent years, along with increases in screen size and improvements in resolution, the driving methods for liquid crystal displays (LCDs) are moving from simple matrix methods to active matrix methods; and the displays are becoming capable of displaying large amounts of information. LCDs with more than several hundreds of thousands pixels are possible with active matrix methods which place a switching transistor at each pixel. Transparent insulating substrates such as fused quartz and glass which allow the fabrication of transparent displays are used as substrates for all types of LCDs. Although ordinarily semiconductor layers such as amorphous silicon or polycrystalline silicon are used as the active layer in thin film transistors (TFTs), the use of polycrystalline silicon which has higher operating speeds is advantageous for the case of producing monolithic displays which include integrated driving circuits. When polycrystalline silicon is used as the active layer, fused quartz is used as the substrate; and a so-called xe2x80x9chigh temperaturexe2x80x9d process in which the maximum processing temperature exceeds 1000xc2x0 C. is used to fabricate the TFTs. On the other hand, for the case of an amorphous silicon active layer, a common glass substrate can be used. For increases in LCD display size while maintaining low costs, such use of low-cost common glass substrates is indispensable. Such amorphous silicon layers, however, have such problems as electrical characteristics far inferior to those of polysilicon layers and slow operating speed. Since the high temperature process polysilicon TFTs use quartz substrates, however, there are problems with increasing display size and decreasing costs. Consequently, there is a strong need for technology which can fabricate a thin film semiconductor device employing a semiconductor layer such as polycrystalline silicon as the active layer upon a common glass substrate. But, when using large substrates which are well-suited to mass production, there is a severe restriction in that the substrates must be kept below a maximum processing temperature of about 570xc2x0 C. in order to avoid deformation of the substrates. In other words, technology which can produce, under such restrictions, the active layer of thin film transistors capable of controlling a liquid crystal display and of thin film transistors which can operate driving circuits at high speed is desired. These devices are currently known as the present low temperature poly-Si TFTs.
Previous low temperature poly-Si TFTs are shown on p. 387 of the SID (Society for Information Display) ""93 Direst (1993). According to this description, 50 nm of amorphous silicon (a-Si) is first deposited at 550xc2x0 C. by LPCVD using monosilane (SiH4) as the source gas and then converted from a-Si to poly-Si by laser irradiation. After patterning of the poly-Si layer, a gate insulator layer of SiO2 is deposited by ECR-PECVD at a substrate temperature of 100xc2x0 C. Following formation of the tantalum (Ta) gate electrode on top of the gate insulator layer, self-aligned transistor source and drain regions are formed in the silicon layer by ion implantation of donor or acceptor impurities while using the gate electrode as a mask. This ion implantation, known as xe2x80x9cion dopingxe2x80x9d, is accomplished by a non-mass separating ion implanter. Hydrogen-diluted phosphine (PH3), diborane (B2H6) or similar gas is used as a source gas for ion doping. Activation of the impurities is carried out at 300xc2x0 C. Following deposition of an interlevel insulator layer, electrodes and interconnects such as indium tin oxide (ITO) and aluminum (Al) are deposited to complete the thin film semiconductor device.
As described below, however, there are several inherent problems with poly-Si TFTs fabricated by the existing technology in the low temperature process which act as impediments to the adoption of this technology into mass production.
1. The high processing temperature of 550xc2x0 C. prevents the use of low-priced glass leading to a steep rise in product prices. Additionally, the degree of warp of the glass substrates as a result of their own weight increases as substrate size increases, and increases in liquid crystal display (LCD) sizes are not possible.
2. The appropriate irradiation conditions necessary to obtain uniform laser irradiation over the entire substrate are severe and fall within a narrow range. As a result, the crystallization of the film can vary from uniform to non-uniform from lot to lot and reliable production is not possible.
3. During the ion doping or subsequent low temperature activation at 300-350xc2x0 C. of the source and drain regions which are self-aligned with respect to the gate electrode, the problem of unsuccessful activation occasionally occurs. In other words, the resistance of the source and drain regions is several gigaohms. Especially when producing TFTs with lightly doped drains (LDD), this problem is serious and is a cause of significant decreases in production yield.
4. Although only SiO2 formed by ECR-PECVD yields suitable transistor properties-in low temperature process poly-Si TFTs, it is difficult to increase the size of the ECR source in the ECR-PECVD equipment thereby making ECR-PECVD unsuitable for large LCD panels. Furthermore, the throughput is extremely poor. Consequently, ECR-PECVD reactors are not suitable as mass production-compatible, practical gate oxide film deposition equipment applicable to the manufacture of large size displays.
5. Use of means such as laser irradiation for melt crystallization of semiconductor films like silicon results in partial agglomeration which can lead to large variations in the electrical properties of the semiconductor layer, roughness of the semiconductor layer, and decreases in the gate-source or gate-drain electrical breakdown strength.
6. When low cost, conventional glass substrates were used, the underlevel protection layer necessary to effectively prevent penetration of impurities from the glass into the semiconductor layer was not the underlevel protection layer of the semiconductor devices which showed the optimum electrical properties. In other words, making the underlevel protection layer thicker to is prevent impurity penetration leads to the deterioration of the electrical properties of the semiconductor device from stress generated by the underlayer or generates cracks in the semiconductor device.
7. When plasma enhanced chemical vapor deposition (PECVD) is used to produce the semiconductor films, elements such as fluorine (F) and carbon (C), constitutive elements of vapors used in cleaning the deposition chamber which may remain after cleaning, may be incorporated as impurities into the films. The result is that the amount of impurities incorporated into the substrates varies, and it is not possible to reliably produce excellent thin film semiconductor devices.
8. As the deposition temperature for semiconductor films in low pressure chemical vapor deposition (LPVCD) decreases, compatibility between uniformity within a substrate and the deposition rate is difficult. In other words, because the deposition rate decreases when the deposition temperature is lowered, the increase in pressure necessary to compensate for this behavior results in significant worsening of the uniformity over a single substrate. This tendency becomes noticeably more pronounced as the substrate size becomes larger and is a major obstacle to the mass production of large LCDs.
9. There are three types of non-uniformity of the electrical characteristics of thin film semiconductor devices. In addition to variations within a single substrate, there are also variations from substrate to substrate in a single lot as well as variations between different lots. In the thin film semiconductor devices and the fabrication procedures of the existing technology, it is not possible to control these three types of non-uniformity. In particular, there has been almost no thought given to the variation in properties seen from lot to lot.
10. In the fabrication of semiconductor thin films by PECVD, the adhesion between the semiconductor layer and the protective underlayer is poor; and numerous crater-shaped holes are generated in the semiconductor layer which can lead to delamination of the film in the worst case.
The present invention aims to solve the problems noted above with the purpose of providing a means for reliably producing good thin film semiconductor devices through a realistically convenient method using a processing temperature which will allow the use of common large glass substrates.
The fundamental principles and operation of the present invention will be explained with reference to the drawings.
FIGS. 1(a) through (d) are cross-sectional schematic representations of the fabrication process for thin film semiconductor devices constituting an MIS field effect transistor. After giving an outline of the low temperature poly-Si TFT fabrication process using these figures, the details of the present invention will be explained for each processing step.
(1, Outline of the Fabrication Procedure of a Thin Film Semiconductor Device of the Present Invention)
In the present invention, a conventional non-alkaline glass is used as an example for substrate 101. First, an insulating underlevel protection layer 102 is formed on top of substrate 101 by a technique such as atmospheric pressure chemical vapor deposition (APCVD), PECVD, or sputtering. Next, a semiconductor layer such as intrinsic silicon, which will later become the active layer of the semiconductor device, is deposited. The semiconductor layer can be formed by chemical vapor deposition (CVD) such as LPCVD, PECVD, or APCVD or by physical vapor deposition (PVD) such as sputtering or evaporation. Crystallization of the semiconductor layer so fabricated is achieved by short -time irradiation using electromagnetic energy or optical energy such as from laser light. When the originally deposited semiconductor layer is amorphous or a mixture of amorphous and microcrystalline material, this process is known as crystallization. On the other hand, if the originally deposited semiconductor layer is polycrystalline, the process is known as recrystallization. In this description of the present invention, both are simply referred to as xe2x80x9ccrystallizationxe2x80x9d unless it is necessary to make a distinction. If the intensity of the energy from laser light or other source is high, the semiconductor layer will crystallize by initially melting and then solidifying upon cooling. This is known as melt crystallization in the present invention. Conversely, crystallization in which the semiconductor layer does not melt but proceeds in the solid state is known as solid phase crystallization (SPC). Solid phase crystallization can be divided mainly into three types: furnace-SPC in which crystallization occurs at temperatures from 550xc2x0 C. to 650xc2x0 C. for times ranging from a few hours to several tens of hours, rapid thermal annealing (RTA) in which crystallization occurs in a very short time frame ranging from less than one second up to about one minute ato temperatures of 700 to 1000xc2x0 C., and very short time-SPC (VST-SPC) using low intensity energy such as from a laser. Although all three types are suitable for use in the present invention, melt crystallization, RTA and VST-SPC are particularly appropriate when considered in light of processing which allows high productivity for large substrates. The reason for this is not only that these crystallization methods use extremely short irradiation periods but also that the whole substrate is not heated during crystallization of the semiconductor layer since the irradiated area is localized with respect to the entire substrate area; and, therefore, no heat-induced deformation or cracking of the substrate occurs. Following crystallization, the semiconductor layer is patterned; and then the active semiconductor layer 103 is produced. See FIG. 1(a).
After formation of the semiconductor layer, the gate insulator layer 104 is formed by a method such as CVD or PVD. Several methods can be considered for the fabrication of insulating films, but a fabrication temperature of 350xc2x0 C. or less is desirable. This is essential to avoid thermal degradation of the MOS interface and the insulating film. This is applicable to subsequent steps in the fabrication process as well. Processing temperatures following fabrication of the gate insulator layer must be kept at or below 350xc2x0 C. Doing so allows high performance semiconductor devices to be produced both easily and reliably.
Next, a thin film which will become the gate electrode 105 is deposited by a method such as PVD or CVD. Since the same material is usually used for both the gate electrode and the gate interconnects and both are fabricated in the same step, it is desirable to use a material which has low electrical resistance and is stable with respect to thermal processing around 350xc2x0 C. After patterning of the thin film for the gate electrode, ion incorporation 106 into the semiconductor layer is employed to form the source and drain regions 107 and the channel region 108. See FIG. 1(c). During this process, the gate electrode acts as a mask for ion implantation so that the channel is formed only underneath the gate in a self-aligned structure. For impurity ion incorporation, both ion doping, in which non-mass separation equipment is used and hydrogenated impurity species as well as hydrogen are incorporated into the film, and ion implantation, in which mass-separation ion implanters are used and only the desired impurities themselves are incorporated into the film, are applicable. Source gases for ion doping use hydrogenated species of the impurity ions such as phosphine (PH3) and diborane (B2H4) which are diluted in hydrogen to concentrations of 0.1% to 10%. In the case of ion implantation, hydrogen ions (protons or molecular hydrogen ions) are implanted following the implantation of the desired impurity elements by themselves. In order to maintain a stable MOS interface and gate insulator layer, the temperature must be kept at or below 350xc2x0 C. for both ion doping and ion implantation. In order to always reliably carry out the impurity activation at a low temperature of 350xc2x0 C. or less, it is desirable to keep the substrate temperature above 200xc2x0 C. during implantation. On the other hand, to ensure a low temperature activation of impurity ions implanted in the channel to control the transistor threshold voltage or impurity ions implanted in lightly doped regions such as those used to form an LDD structure, it is necessary to keep the substrate temperature at or above 250xc2x0 C. during ion implantation. The result is that amorphization of the ion implanted region can be avoided by performing the ion implantation at a such a high substrate temperature since recrystallization occurs simultaneously with damage to the semiconductor layer. In other words, the ion implanted region remains crystalline following implantation, and the subsequent activation of the implanted ions can still be achieved using a low activation annealing temperature of less than about: 350xc2x0 C. When fabricating a CMOS TFT, the NMOS or PMOS region is alternately covered by a suitable mask material such as polyimide resin, and ion implantation is performed using the procedure above. If the substrate temperature is kept below approximately 300xc2x0 C. during ion implantation, it is possible to use a cheap, easily preserved conventional photoresist as an ion implantation mask instead of the polyimide.
Next, the interlevel insulator film 109 is formed by either CVD or PVD. Following ion implantation and interlevel insulator film formation, ion activation and interlevel insulator film densification are carried out by thermal annealing in a suitable thermal environment at temperatures less than about 350xc2x0 C. for a time ranging from several tens of minutes to a few hours. It is is desirable for this annealing temperature to be greater than approximately 250xc2x0 C. to ensure activation of the implanted ions. Additionally, for effective densification of the interlevel insulator film, a temperature of 300xc2x0 C or higher is preferred. The film quality of the gate insulator layer and the interlevel insulator layer are normally different. Accordingly, during the opening of contact holes in the two insulator films following interlevel insulator film formation, it is common for the etching rates in the two films to be different. Under such conditions, an inverse taper in which the bottom of the contact hole is wider than the top or the formation of a canopy can result. During electrode formation, these undesirable structures can be causes of poor contact between the electrode and underlying layers in the device leading to so-called xe2x80x9ccontact failure.xe2x80x9d The generation of contact failure can be minimized by effective densification of the interlevel insulator film. Following formation of the interlevel insulator layer, contact holes are opened above the source and drain regions; and source and drain electrodes 110 and interconnects are formed by PVD or CVD to complete the fabrication of the thin film semiconductor device. See FIG. 1(d).
(2, Detailed Explanations of the Individual Steps in the Fabrication Process of the Thin Film Semiconductor Device of the Present Invention)
(2-1, Substrates and Underlevel Protection Layers Suitable for the Present Invention)
First, substrates and underlevel protection layers suitable for the present invention will be explained. For the present invention, substrates including conductive materials such as metals; ceramic materials such as silicon carbide (SiC), alumina (Al2O3), and aluminum nitride (AlN); transparent insulating materials such as fused quartz and glass; semiconductor substrates such as silicon wafers or processed LSI; and crystalline insulators such as sapphire (trigonal Al2O3) can be used. Low priced conventional glass substrates which can be used include Corning Japan""s 7059 and 1737 glasses, Nippon Electric Glass Co., Ltd.""s OA-2 glass, and NH Techno Glass""s NA35. The type of substrate is immaterial for the semiconductor film; and, as long as least part of the substrate surface is composed of an insulating material, the semiconductor layer can be deposited on top of the insulating material. This insulating material is known as the underlevel protection layer in the present invention disclosure. For example, if a fused quartz substrate is used as a substrate, it is acceptable to deposit a semiconductor film directly on top of the fused quartz substrate since the substrate itself is insulating. Or, it is acceptable to deposit the semiconductor film on top of an underlevel protection layer such as silicon oxide (SiOx: 0 less than xxe2x89xa62) or silicon nitride (Si3Nx: 0 less than xxe2x89xa64) which has been formed on top of the quartz substrate. When using an ordinary glass substrate, it is possible to deposit the semiconductor film directly on top of the insulating glass, but it is desirable to deposit the semiconductor film after the formation of an insulating underlevel protection layer such as silicon oxide or silicon nitride to avoid penetration of mobile ions like sodium (Na), which are contained in the glass substrate, into the semiconductor film. By so doing, the operational properties of the semiconductor device do not vary under operation over a long time period or under high voltages, and the stability is increased. In the present invention, this stability is called transistor reliability. With the exception of using crystalline insulating materials such as sapphire as substrates, it is desirable to deposit the semiconductor film on top of an underlevel protection layer. When using any type of ceramics as a substrate, the underlevel protection layer serves to prevent sintering aids added to the ceramics from diffusing into the semiconductor regions. In the case of metallic substrates, the use of an underlevel protection layer is essential to maintain the insulating properties. Further, with semiconductor substrates or LSI elements, interlevel insulator films between transistors or between interconnects serve the role of underlevel protection layers. The substrate size and shape adds no additional restrictions as long as the substrates do not shrink or distort in the thermal environment during processing. Substrates can be anywhere on the order of 3 inch diameter (76.2 mm) disks to 560 mmxc3x97720 mm rectangular plates.
After the substrate has been cleaned in deionized water, an underlevel protection layer of an oxide such as silicon oxide, aluminum oxide, or tantalum oxide; or a nitride such as silicon nitride is formed on the substrate by CVD methods such as APCVD, LPCVD, or PECVD; or by PVD methods. Oxides and nitrides can be formed by initially forming a metallic layer such as silicon, aluminum, or tantalum on the substrate and then using a thermochemical or electrochemical reaction. For example, it is possible to form an approximately 200 nm thermal tantalum oxide film by first sputtering about 100 nm of tantalum and then heating in an oxidizing atmosphere at about 450xc2x0 C. to achieve thermal oxidation. Using APCVD, it is possible to deposit a silicon oxide film using monosilane (SiH4) and oxygen as source gases at a substrate temperature of about 250 to 450xc2x0 C. PECVD and sputtering can form underlevel protection layers using substrate temperatures between room temperature and approximately 400xc2x0 C.
In the present invention, because the semiconductor layer formed on top of the underlevel protection layer functions as the active layer for the transistor and this semiconductor layer is formed by crystallization, the properties of the underlevel protection layer have a strong influence on the quality of the semiconductor layer. First, it is desirable to have the center line mean surface roughness of the underlevel protection layer be 3.0 nm or less. When a semiconductor film such as silicon is deposited by CVD on top of an underlevel protection layer, the very first stage in film formation is the generation of many nuclei on top of the substrate. While these nuclei gradually grow, new nuclei form at sites on the underlevel protection layer which are not yet populated by nuclei. All of these nuclei grow, impinge on each other, and eventually link to form a film. Regardless of whether the film is amorphous or crystalline, all deposited films, having their origin in such growth mechanisms, are constructed from regions corresponding to nuclei in the early stages of growth. Consequently, if the nuclei density is low, the regions constituting the film will become large. If the regions in the semiconductor film prior to crystallization are large, the grains constituting the crystallized film will also be large. When the grains in the semiconductor film are large, the electrical properties, such as mobility, of the semiconductor device having an active layer comprised of these grains improve. According to the experiments of the inventor, it has become clear that the nuclei density can be kept low if the center line mean surface roughness is about 3.0 nm or less with the result being the ability to fabricate high performance semiconductor devices. The reason for this seems to be that the irregularity in the surface of the underlevel protection layer is one factor in nucleation, and the nucleation density increases as the surface irregularity becomes more pronounced. Further, it is desirable to have the center line mean surface roughness of the underlevel protection layer be about 1.5 nm or less when the semiconductor layer is melt crystallized. If the surface is this smooth, the melted semiconductor material such as silicon spreads readily over the underlevel protection layer. Because of this, large diameter grains can grow easily; and the properties of the thin film semiconductor device are improved dramatically. At the same time, local agglomeration of the molten material during solidification of the melted semiconductor material does not occur; and the uniformity within the molten region increases. The LSI scaling law applies to thin film semiconductor devices as well; and it appears that the miniaturization of elements will continue in step with future integration. As transistor sizes continue to shrink from the 1 xcexcm order to submicron order, how to avoid local agglomeration will be an important issue. When fabricating the semiconductor layer by melt crystallization, the center line mean surface roughness of the underlevel protection layer is ideally 1.0 nm or less. By meeting this criterion, it is possible to produce uniform films, without local agglomeration, from semiconductor films with large-diameter grains.
Another role of the underlevel protection layer is to prevent the diffusion of impurity elements from the substrate. To do so, it is effective to combine at least two or more different types of films in a layered structure to act as the underlevel protection layer. For example, a layered structure comprising, from the substrate, a tantalum oxide film, a silicon nitride film, and a silicon oxide film can be used. There are various types of impurity elements in normal substrates, and these elements have different diffusion coefficients in the different insulators mentioned above. It is easily possible to have a certain impurity element which diffuses slowly through one of the layers comprising the underlevel protection layer but diffuses quickly through another layer. There are various impurity elements contained within substrates; and, since there is a fixed underlevel protection layer thickness as will be explained later, underlevel protection layers formed by layering of different layers are more effective in preventing the diffusion of impurities than single layers. Many different materials can be considered for the underlevel protection layer; but, from the viewpoint of ease of fabrication by processes such as CVD, composite layers of silicon nitride and silicon oxide are the most appropriate. In such two-layer composite or multilayer composite underlevel protection layers, it is desirable to have the upper most layer be of silicon oxide. This is because the interface states which are inevitably generated between the underlevel protection layer and the semiconductor layer are minimized using silicon oxide. Especially for thin semiconductor films less than a few hundred nm in which the depletion layer formed under the transistor operating conditions can consume the entire semiconductor layer thickness, it is essential to suppress such interface states. In the present invention, the optimum semiconductor film thickness for the thin film semiconductor device varies slightly depending on the fabrication process but is less than approximately 150 nm. Nevertheless, because the quality of the semiconductor film is high, there are few grain boundary trapping states-and few intragranular defects on account of this, the depletion layer extends completely through the semiconductor film when the transistor is in operation. If there are many interface states generated at the interface between the underlevel protection layer and the semiconductor layer, the spread of the depletion layer during channel formation is delayed, leading to a high threshold voltage since the interface states effectively act the same as donor and acceptor ions. In other words, these interface states can become one factor in the degradation of transistor properties. The effect of the surface of the underlevel protection layer on transistor properties appears when the semiconductor layer is less than approximately 150 nm thick, and when the effective doping concentration in the channel layer {[(acceptor ion concentration)xe2x88x92(donor ion concentration)+(concentration of trapping states and crystal defects acting as acceptor ions)] for the case of NMOS; [(donor ion concentration)xe2x88x92(acceptor ion concentration)+(concentration of trapping states and crystal defects acting as donor ions)] for the case of PMOS} is less than about 1xc3x971018 cmxe2x88x923, or when the threshold voltage of the thin film semiconductor device is less than approximately 4.5 V. To restore the properties of transistors satisfying these conditions, it is imperative to control the surface of the underlevel insulator layer; and one way to do this is to use silicon oxide as the top layer in a mutilayer underlevel protection layer composite.
It is necessary to have a sufficiently thick underlevel protection layer to prevent the diffusion of impurity ions from the substrate into the semiconductor device, and this thickness is on the order of 100 nm as a minimum. Considering variations from lot to lot or from wafer to wafer within a single lot, it is better to have a thickness greater than 200 nm; and, if the thickness is 300 nm, the film can function sufficiently as a protection layer. When the underlevel protection layer also serves as an interlevel insulator layer between IC elements or the interconnects connecting such elements, a thickness of from 400 to 600 nm is common. Since too thick of an insulating layer is a cause of stress which can lead to cracking, however, a maximum thickness of about 2 xcexcm is preferable. Consideration of throughput, however, reduces the maximum thickness to 1 xcexcm. For the case mentioned previously of a composite interlevel protection layer comprising a bottom layer of silicon nitride and a top layer of silicon oxide, the same relations hold; and it is necessary to have a total thickness of 100 nm with each layer 50 nm thick. In the thin film semiconductor device of the present invention, the gate insulator layer is formed by CVD or PVD at a temperature below about 350xc2x0 C. To obtain a clean MOS interface for this process, the native oxide layer on the semiconductor layer surface is removed immediately prior to gate oxide film formation. This native oxide removal step does not remove only the native oxide on the surface of the semiconductor layer, but also unfortunately removes part of the exposed underlevel silicon oxide layer surface not covered by the semiconductor layer. Even after the native oxide removal step, there must be 100 nm or more of the underlevel protection layer silicon oxide for the layer to function properly. In other words, the minimum thickness of the silicon oxide layer is about 100 nm, and the minimum thickness of the silicon nitride is about 50 nm. For a thickness of less than 50 nm, the film islands do not link to form a complete film leaving gaps sporadically throughout the film. Since an underlevel protection layer loses its ability to prevent diffusive impurity penetration, it is necessary to have a minimum film thickness of 50 nm even when several films are used. As mentioned previously, the upper limit on the thickness of silicon nitride and silicon oxide films is 2 xcexcm. Because an underlevel protection layer film thickness of 300 nm is sufficient and thicker films actually are stressed leading to cracking or degradation of transistor properties, the ideal upper limit is approximately 500 nm. When several layers are combined in a composite layered structure, the stress conditions from each film are different; and if the thicknesses of all films are kept below about 500 nm, there should be no problems.
In general, silicon oxide films deposited by CVD or PVD at temperatures less than about 350xc2x0 C. have high internal stress. It is common to relieve a portion of such stress by high temperature thermal annealing following deposition. In the low temperature process of the present invention, however, the maximum processing temperature must be kept below about 350xc2x0 C. following gate insulator formation. Since it is difficult to relieve stress in a silicon oxide film subjected to only such a low temperature anneal, silicon oxide films thicker than about 2 xcexcm can lead to cracks in the substrate. Additionally, along with increases in substrate size such as those greater than 300 mxc3x97300 mm, it becomes easier for stresses to accumulate and induce cracking in the substrate. The conditions are the same regardless of whether the silicon oxide film is a single layer or a composite structure, and cracks are generated if the total silicon oxide film thickness is 2 xcexcm or more. In the thin film semiconductor device of the present invention, an underlevel protection layer of an insulating material is deposited on a portion of the substrate; and this is followed by fabrication of a field effect transistor, comprising a semiconductor layer, gate insulator, and gate electrode, on top of the underlevel protection layer. This is then followed by formation of an interlevel insulator layer between the interconnects of the field effect transistor to achieve electrical isolation. In addition to at least the upper-most layer of the underlevel protection layer being of silicon oxide, so is the MOS interface part of the gate insulator; and it is normal to also use silicon oxide in at least a portion of the interlevel insulator layer. Consequently, if the sum of the thicknesses of these three types of silicon oxide is less than 2 xcexcm, formation of a thin film semiconductor device by the low temperature process on large substrates is possible without inducing cracking, of course, it is possible to effectively prevent the generation of cracks if the sum of the thicknesses of the underlevel protection layer, the gate insulator layer, and the interlevel insulator layer is less than 2 xcexcm.
As was explained previously in the reason for preferring the top layer of the underlevel insulator layer to be of silicon oxide, when using a high-quality semiconductor film for the active layer such as in the thin film semiconductor device of the present invention, control of the interface between the semiconductor layer and the underlevel protection layer is important. Particularly when forming the semiconductor layer using melt crystallization, it is desirable to have the surface of the underlevel protection layer be as clean as possible. If the underlevel protection layer surface is clean, this not only reduces the number of interface states between the semiconductor layer and the underlevel protection layer, but also prevents particulate or other contaminants from being incorporated into the semiconductor layer during the melt crystallization step. Therefore, it is beneficial if the underlevel protection layer and the semiconductor layer can be formed sequentially in the same piece of equipment. If the underlevel protection layer is silicon nitride, silicon oxide or a double layer of both, and the semiconductor layer is a silicon or silicon germanium film, it is possible to sequentially form such layers using a single PECVD reactor. If the mass production of thin film semiconductor devices is considered, the deposition chamber for these films are periodically cleaned; and it is necessary to remove the films which have adhered inside the PECVD deposition chamber. If cleaning is not carried out and the films continue to adhere, the films may eventually peel off and fall or lead to generation of abnormal microparticles which result in significant decreases in production yield. On the other hand, however, during the cleaning step to remove deposited thin films from the deposition chamber, trace amounts of constituent elements from the cleaning vapors such as fluorine (F) and carbon (C) are sure to be left behind in the deposition chamber. Under these conditions, the trace elements can be incorporated as impurities into the semiconductor film during the deposition process and cause degradation of the transistor properties. Additionally, if the cleaning process is repeated after a set number of substrates have been processed, the amount of impurities incorporated into substrates just after the cleaning step will be large while the amount incorporated into substrates just before the cleaning step will be small. Put another way, the amount of impurities incorporated will differ from substrate to substrate; and it will not be possible to reliably produce excellent thin film semiconductor devices. Consequently, in the present invention, the cleaning process is performed as part of the sequential deposition of the films described earlier. In other words, the cleaning process is included with the film deposition process for each substrate. As the first step, prior to placing the substrate in the PECVD reactor, the deposition chamber is cleaned of any films which were deposited during processing of the previous substrate. Specifically, cleaning gases such as NF3, CF4, CHF3, CH2F2, and CH3F are introduced into the deposition chamber separately, or in combination with such reaction-controlling gases as oxygen (O2), hydrogen (H2), or ammonia (NH3); or, as need be, with such inert gases as helium (He), argon (Ar), or nitrogen (N2); and a plasma is initiated. Thin films deposited in the deposition chamber are removed in this step. Following completion of this cleaning procedure, a vacuum is pulled on the chamber to remove as much of the remaining gas vapors as possible. Next, in step two, a silicon nitride or silicon oxide passivation layer for the remaining impurity elements is deposited. The impurity elements, in other words, are sealed in by the passivation layer. As for the case of the underlevel protection layer, a passivation layer of more than 100 nm will effectively prevent the penetration of the impurities. It is necessary to completely remove this passivation layer after the processing of each substrate. Therefore, since making the film too thick will slow down the manufacturing process by increasing both the time for removal in step one and the time for deposition in step two, the upper limit for the passivation film thickness is approximately 1 xcexcm. When silicon nitride is used as the passivation film, ammonia (NH3) and silane (SiH4, Si2H6, etc. ) are used as source gases. For silicon oxide passivation layers, nitrous oxide (N2O) and silane are used. Following placement of the substrate in the deposition chamber in step three, the underlevel protection layer is grown on the substrate in step four. The deposited layer functions as the underlevel protection layer on top of the substrate but functions as a second passivation layer on areas in the deposition chamber away from the substrate. Because the underlevel protection layer by itself is able to prevent the diffusion of impurities within the underlevel layer, when combined with the passivation layer deposited in step two, it is able to almost completely prevent the incorporation of impurities into the semiconductor layer. Following step four, the semiconductor layer is grown in step five without breaking vacuum; and the processing of a single substrate is completed with removal of the substrate from the deposition chamber in step six. The same procedure is repeated for each subsequent substrate. By following this substrate processing procedure and sequentially depositing the underlevel protection layer and the semiconductor layer, it is possible to keep the interface between the underlevel protection layer and the semiconductor clean and fabricate excellent thin film semiconductor devices. Further, it is possible to keep the amount of impurities such as fluorine and carbon incorporated in the semiconductor layer to a minimum. Even if there are minute amounts within the films, since it is possible to always keep the amount constant, the result is the ability to reliably produce excellent thin film semiconductor devices in a high productivity process.
(2-2, Semiconductor Films in the Present Invention and the Source Gases used to Grow Them)
In the present invention, semiconductor films are deposited on some type of substrates. This is a feature common to all the following inventions. In addition to being applicable to single element films such as silicon (Si) and germanium (Ge), the following types of semiconductor films are also possible: group IV compound semiconductor films such as silicon germanium (SixGe1xe2x88x92x: 0 less than x less than 1) , silicon carbide (SixC1xe2x88x92x: 0 less than x less than 1), and germanium carbide (GexC1xe2x88x92x: 0 less than x less than 1); III-V compound semiconductor films such as gallium arsenide (GaAs), and indium antimonide (Insb); II-VI compound semiconductor films such as cadmium selenide (CdSe). The present invention is also applicable to higher compound semiconductor films such as silicon germanium gallium arsenide (SixGeyGazAsz: x+y+z=1) as well as N-type semiconductor films in which donor elements such as phosphorous (P), arsenic (As), or antimony (Sb) have been added and P-type semiconductors in which acceptor elements such as boron (B), aluminum (Al), gallium (Ga), and indium (In) have been added.
When semiconductor films are deposited by CVD in the present invention, the films are deposited using as source gases chemical species containing the constitutive elements of the films. For example, when the semiconductor film is silicon (Si), a silane such as monosilane (SiH4), disilane (Si2H6), trisilane (Si3H8), or dichlorosilane (SiH2Cl2) is used as a source gas. In the present invention disclosure, disilane and trisilane are called higher silanes (SinH2n+2: n is an integer greater than or equal to 2). If germanium (Ge) is the semiconductor film, germane (GeH4) is used; and phosphine (PH3) and diborane (B2H6) can be used in addition if phosphorous (P) or boron (B) are to be added to the semiconductor film. Although chemical species containing the constitutive elements of the various types of films mentioned above can be used as source gases, it is preferable to use hydrogenated species of the constitutive elements since some of the source gases will always be incorporated into the semiconductor film. For example, silicon films grown from dichlorosilane (SiH2Cl2) will always contain some chlorine (Cl) whether in small or large amounts; and this incorporated Cl can lead to the degradation of transistor properties when the silicon film is used as the active layer in a thin film semiconductor device. Therefore, monosilane (SiH4), a hydrogenated form of the constituent element, is preferable over dichlorosilane. As high a purity as possible for the source gases, and dilution gases if need be, is desirable. Considering that costs increase as the technological difficulties in producing high purity gases grow, a purity of 99.9999% or higher is desirable. The background pressure of common semiconductor film deposition equipment is on the order of 10xe2x88x926 torr, and the process pressure is from 0.1 torr to a few torr. Therefore, the ratio of the incorporation of impurities from the background pressure in the film growth step is on the order of 10xe2x88x925 to 10xe2x88x926. The purity of the source or dilution gases is sufficient if it is equivalent to the ratio of the process pressure to the background pressure of the equipment using the gases. As a result, a purity of 99.999% or more (impurity ratio of 1xc3x9710xe2x88x925 or less) for gases flowing in the deposition equipment is desirable in the present invention. If the purity is 99.9999% (impurity ratio of 1xc3x9710xe2x88x926 or less), there is absolutely no problem for use as a source gas; and, in the ideal case in which the purity is ten times that of the ratio of the background pressure to the process pressure (99.99999% in the present example; impurity ratio of 1xc3x9710xe2x88x927 or less), the incorporation of impurities from the gases need not even be considered.
(2-3, LPCVD Reactor used in the Present Invention)
The LPCVD reactor used in the present invention to deposit semiconductor films by the LPCVD process will be explained. The LPCVD reactor can be either of the vertical or horizontal furnace type . Generally, the deposition chamber is made of quartz or like material, and the substrates are placed near the center region of the deposition chamber. The outside of the deposition chamber is divided into multiple zones with heaters located in each zone. A uniform thermal region is created at the desired temperature in the region around the center portion of the reaction chamber by using these heaters which can be independently controlled. This is a so-called hot wall LPCVD reactor. By independently controlling the individual heaters, it is possible to keep the temperature variation within the uniform thermal region to within 0.2xc2x0 C. Even though this temperature variation is very slight, it is always present, and is the leading cause of variations in film thickness. Additionally, since film thickness uniformity over one substrate is given preference over film thickness from substrate to substrate, it is desirable to set the substrates parallel with respect to the radial heating direction of the heaters. For example, for a vertical furnace LPCVD reactor, the semiconductor film thickness is more uniform when the substrates are placed approximately horizontal as opposed to when they are placed vertically. Conversely, for a horizontal reactor, it is better to place the substrates approximately vertically. The source gases such as silane (SiH4), disilane (Si2H6), or germane (GeH4) and, when need be, dilution gases such as helium, nitrogen, argon, and hydrogen enter the deposition chamber from a gas introduction port set up in a given direction. After depositing a semiconductor layer on the multiple substrates set in the central region of the deposition chamber as well as on the side walls of the deposition chamber, the gases are exhausted from a location opposite to that of the entrance port. The gases are pumped through a gate valve or a conductance valve by a pumping system which may consist of a turbomolecular pump and a rotary pump, for example. In the present invention, the pumping system consists of a turbomolecular pump and a rotary pump; but combinations with mechanical booster pumps or dry pumps are also acceptable. Regardless of whether the reactor is vertical or horizontal, it is relatively simple to achieve uniformity of the semiconductor film by basically aligning the direction of gas flow in the deposition chamber with the direction normal to the substrates set in the deposition chamber. In other words, in the case of a vertical reactor, it is preferable to have vertical gas flow since the substrates are placed approximately horizontally as mentioned previously. In a similar fashion, it is preferable to have horizontal gas flow in a horizontal reactor because the substrates are placed vertically. The LPCVD reactor used in the present invention is a high vacuum reactor with a background pressure in the 10xe2x88x927 torr range. Consequently, it is possible to pump the inevitable outgassing from the substrates and substrate boat at a sufficient rate. The outgassing impurity species from the substrate and boat, which include water and oxygen among others, are impediments to the growth of good semiconductor films. These outgassing impurities from the substrates and boat can become nuclei for the deposited film during the initial stages of deposition of a silicon or other type of semiconductor film. If the outgassing is not exhausted sufficiently, there will be a large amount of adsorbed impurity gases on the substrate surface leading to the generation of many nuclei. Even when the semiconductor film is crystallized by thermal annealing or laser irradiation-following deposition, the presence of the many nuclei resulting from the outgassing will result in the average grain size of the crystallized film being small and cause a degradation in the transistor properties. Additionally, the trapping of outgassing impurities in the semiconductor film during growth leads to further decline in transistor properties. As explained in section (2-1), the film quality and surface roughness of the underlevel protection layer play an important role in suppressing the generation of nuclei. At the same time, the deposition conditions of the semiconductor film must also be carefully controlled. Consequently, in addition to the regulation of the surface of the underlevel protection layer in order to minimize the generation of nuclei, the use of an LPCVD reactor which can sufficiently pump the unavoidable outgassing from the substrates and the surrounding surfaces is indispensable.
In LPCVD, semiconductor films are deposited on top of substrates using thermal decomposition of the source gases. The two biggest issues in using LPCVD to fabricate films on large substrates such as those 300 mmxc3x97300 mm at relatively low temperatures while maintaining high productivity are the deposition rate (DR) and the uniformity. For example, consider the deposition of a silicon layer on a large area, conventional, low cost glass substrate as mentioned previously. For substrates 300 mmxc3x97300 mm or larger, distortion of the substrate from its own weight will occur during film growth, regardless of the setting of the substrate, unless the deposition temperature is kept below about 450xc2x0 C. It goes without saying that such thermal distortion decreases for lower deposition temperatures; but for the distortion to decrease to such an extent that it has absolutely no effect on later process steps such as exposure during patterning, the deposition temperature must be less than about 430xc2x0 C. Although semiconductor films such as silicon are deposited at a low temperature of 425xc2x0 C. using higher silanes like disilane, decreasing the deposition temperature to such levels results in an extremely low deposition rate. Therefore, in order to obtain a high deposition rate even at such a low deposition temperature, the deposition pressure is increased. Since gas density is proportional to pressure, an increase in deposition pressure is equivalent to an increase in the source gas density. The result is an increased rate of transport of the source gases over the substrate surface and hence a higher deposition rate. Unfortunately, however, using such a deposition procedure causes the outer region of large substrates to be especially thick; and the result is a deterioration in the film uniformity over the surface of the substrate. The difference in film thickness between the central and outer portions of the substrate becomes conspicuous as the substrate size increases as well as when the deposition temperature decreases. One reason for this seems to be the generation of turbulence at the substrate edge when the rate of source gas transport increases. As a result of the turbulence, a significantly large amount of gas is transported to only is the edge regions with the final result being that the film is thicker along the edges as compared to the central portion of the substrate. Another reason seems to be that the transport rate of the gases to the center of the-substrate decreases as the substrate size increases. In other words, in order to obtain both a high deposition rate and uniform film thickness distribution at low temperatures less than 450xc2x0 C. or less than about 430xc2x0 C., it is essential to always have a high gas phase transport rate regardless of whether it is at the edge or center of the substrate as well as to minimize the generation of turbulence at the substrate edge. The inventor has performed a series of experiments which has shown that for a vacuum level characterized by a source gas partial pressure (disilane partial pressure if disilane is the source gas) of between about 10 mtorr and 5 torr during deposition, the degree of turbulence and differences in transport rate are dependent upon the spacing, d, between substrates in the LPCVD reactor and can be controlled to a certain degree. In the experiments, it was recognized that film thickness uniformity generally tended to improve as the substrate spacing d increased; and, further, that in order to obtain the same level of uniformity for larger substrates, an even larger substrate spacing was necessary. It appears that the uniformity improved as a result of two phenomena. As the substrate spacing was increased by a certain degree, there was an increase in effective gas transport to the center region, and the difference in the amount of transport between the central and outer regions decreased. Additionally, the generation of turbulence at the substrate perimeter also decreased. Specifically, in the deposition temperature range of about 410xc2x0 C. to 440xc2x0 C., film thickness uniformity can be improved by satisfying the conditions of equation (1) shown below for substrates having an area greater than or equal to about 90000 mm2 (substrate size of 300 mmxc3x97300 mm):
dxe2x89xa70.02xc3x97Sxc2xd(mm)xe2x80x83xe2x80x83(1).
For example, a substrate spacing d of 6 mm or more for 300 mmxc3x97300 mm substrates in a LPCVD reactor is good. Excluding the outer 1 cm of 300 mmxc3x97300 mm substrates, the variation in film thickness was 3.4% when the substrates were set 7.5 mm apart in an LPCVD reactor for the following deposition conditions: actual deposition temperature of 425xc2x0 C., disilane flow rate of 200 sccm, helium flow rate of 1000 sccm, pressure of 1.2 torr, disilane partial pressure of 200 mtorr, and a deposition rate of 0.85 nm/min. (Film thickness variation is defined as (maxxe2x88x92min)/(max+min) in which max and min are the maximum and minimum film thicknesses, respectively, in the 280 mmxc3x97280 mm area of the substrate which excludes the outer 1 cm around the perimeter.) In contrast, a film thickness variation of 8.9% was obtained for the same-size substrates under the exact same deposition conditions when the substrates were placed 5 mm apart in the LPCVD reactor. As will be explained in another section, the semiconductor film thickness has a strong influence on the performance of the thin film semiconductor devices. As long as the film thickness variation is less than about 5%, however, there is essentially no problems in variation of device performance. In a similar manner, while a film thickness variation of 4.2% was obtained when 360 mmxc3x97465 mm substrates were loaded in the LPCVD reactor with a spacing of 10 mm, the variation was 10.1% for a spacing of 7.5 mm. According to equation (1), a substrate spacing of greater than or equal to 8.2 mm is necessary for 360 mmxc3x97465 mm substrates; and this is faithfully supported by the actual results. In this manner, a reactor with a 120 cm wide uniform thermal zone can process 100 substrates if the substrates are spaced 10 mm apart even if dummy substrates are placed one each at the top and bottom (or front and back). As will be explained in the following section, the processing time for one batch using the deposition procedure in this invention is on the order of 3 hours. Consequently, the processing time for a single substrate (called the tact time in this invention) is one minute and 48 seconds. When LPCVD reactor maintenance and down time is added, the tact time becomes 2 minutes. In other words, it is possible to fabricate thin film semiconductor devices with good thickness uniformity and high productivity.
As mentioned previously, a decrease in deposition temperature accompanies a decrease in deposition rate and makes the attainment of uniformity difficult. If the deposition temperature is less than about 410xc2x0 C., equation (2) below replaces equation (1):
dxe2x89xa70.04xc3x97Sxc2xd(mm)xe2x80x83xe2x80x83(2).
If the substrates are set according to equation (2), good uniformity is possible just as in the case of equation (1). As shown in FIG. 3(a), when two substrates are placed back-to-back in a vertical configuration as one pair in a horizontal LPCVD reactor for deposition of a semiconductor film, the distance between adjoining pairs corresponds to the substrate spacing d. Considering the previous example of 360 mmxc3x97465 mm substrates, it becomes possible to process 200 substrates in a single batch; and, further, the productivity is increased by a factor of two. A similar relationship holds for vertical LPCVD reactors. In this case as well, two glass substrates are placed back-to-back as one pair and set approximately horizontal. In other words, in one pair of glass substrates, the front of the lower substrate is facing down while the front of the upper substrate is facing up. As for the case of the horizontal reactor, the spacing between pairs of substrates corresponds to the substrate spacing d. See FIG. 3(b). FIG. 4 shows one problem which occurs when large substrates are set horizontally in a hot-wall vertical LPCVD reactor. The center region of the substrate warps. This warp increases as the substrate size increases and also increases for lower glass strain point substrates. Conversely, high strain point glass substrates with good thermal resistance tend to have higher prices. As shown in FIG. 3(b), when setting several glass substrates in two-substrate pairs in an LPCVD reactor, semiconductor films are deposited using substrates with different strain points paired together with the high strain point glass substrate used on the bottom. Because the high strain point glass has little warp, the low strain point glass substrate placed on top can also be made to have little warp using this technique. As a result, it is possible to use even cheaper glass substrates. That is, pairing two glass substrates not only simply increases the productivity by a factor of two, but also allows the price of one LCD to be easily reduced.
(2-4, LPCVD Semiconductor Film Deposition using the Present Invention)
As explained in the preceding section, a deposition temperature which is as low as-possible is desirable for use with conventional, large area glass substrates. A decrease in deposition temperature, however, also means a decrease in deposition rate. In addition to the obvious decrease in productivity which results from the longer time necessary for film deposition with a lower deposition rate, a slower deposition rate also has deleterious effects on thin film semiconductor device performance. Put another way, in the fabrication of a good thin film semiconductor device with a silicon-containing semiconductor layer by the low temperature process, when depositing the semiconductor film using disilane or a higher silane at a deposition temperature less than 450xc2x0 C., especially less than or equal to approximately 430xc2x0 C., if the deposition rate is about 0.20 nm/min or higher, a high mobility thin film semiconductor device can be achieved. Further, if the deposition rate is about 0.60 nm/min or more, it is possible to decrease the variation of transistor properties within a single substrate. Additionally, it is possible to fabricate a thin film semiconductor device having good transistor properties using a poly-Si TFT in which the gate SiO2 insulator layer is formed without the use of ECR-PECVD, and in which the pure silicon semiconductor film is deposited at a deposition temperature less than about 430xc2x0 C. with a deposition rate of about 0.20 nm/min or more and is stable with respect to laser variations during melt crystallization. In fact, amorphous silicon films deposited at a deposition temperature of 400xc2x0 C., disilane flow rate of 200 sccm, helium flow rate of 1000 sccm, pressure of 880 mtorr, disilane partial pressure of 147 mtorr, and a deposition rate of 0.12 nm/min as well as those deposited at a deposition temperature of 425xc2x0 C., disilane flow rate of 200 sccm, hydrogen flow rate of 200 sccm, pressure of 131 mtorr, disilane partial pressure of 65.5 mtorr, and a deposition rate of 0.19 nm/min showed black spots throughout transmission electron micrographs and had small grain sizes following crystallization by RTA. As a result, the mobilities were also low when these films were employed as the active layer in transistors. Although the details may not be certain, the following explanation may explain why black spots are seen in transmission electron micrographs and transistor properties degrade when films are deposited with a deposition rate less than 0.20 nm/min. Perhaps if the growth rate is excessively slow, the surface of the growing film is exposed for a longer time to the gas phase with the result being that more impurities from the background vacuum are incorporated. Therefore, the lower limit of the deposition rate depends on the background pressure in the LPCVD reactor. In other words, in an LPCVD reactor with a background pressure of 1xc3x9710xe2x88x927 torr to 1xc3x9710xe2x88x926 torr such as the one in the present invention, a good semiconductor film can be deposited if the deposition rate is greater than or equal to 0.20 nm/min. If the deposition rate becomes greater than or equal to 0.60 nm/min, the effects from gas impurities disappear completely; and the amount of variation in transistor properties decreases as well. Further, as will be explained later, the optimum film thickness of the semiconductor film for a thin film semiconductor device formed by LPCVD in the present invention is about 50 nm. Therefore, the deposition time is on the order of 80 minutes for a deposition rate greater than or equal to 0.60 nm/min. Including the approximately 20 minutes necessary to insert the substrates in the LPCVD reactor and pull a vacuum, the approximately one hour for preliminary heating prior to film growth, the aforementioned one hour and 20 minutes for deposition, and the approximately 20 minutes necessary for pulling a vacuum after film growth and unloading the substrates, the total processing time for one batch is about three hours. As shown in the previous section, the tact time for processing a batch of 100 substrates is about two minutes; and extremely high productivity with a tact time of less than one minute can be realized if the method of pairing two substrates together is used.
As has been explained in the preceding sections, in order to reliably fabricate a high performance poly-Si TFT on large substrates with the low temperature process, a silicon-containing semiconductor film deposition temperature of less than approximately 430xc2x0 C., deposition rate greater than or equal to 0.6 nm/min, and a film thickness variation of less than about 5% over a large substrate are ideally required. For the case in which a higher silane such as disilane is used as the source gas in film formation using LPCVD, these conditions can be satisfied by a providing a relationship between the total surface area A (cm2) inside the LPCVD reactor which can be covered with the semiconductor film and the flow rate Q (sccm) of the higher silane introduced into the deposition chamber during growth. In other words, by controlling the higher silane flow rate per unit area, R (sccm/cm2) which is given by
R=Q/A,
it is possible to satisfy the three ideal conditions mentioned above. In the growth of semiconductor films by LPCVD, the deposition temperature mainly determines the chemical reaction rate at the surface of the substrates. On the other hand, there is a positive correlation between the spatial concentration of the source gas and the rate of transport of the source gas in the gas phase. The concentration of the source gas C is related to the source gas pressure P and the temperature Tg by
C=P/kTg
in which k is the Boltzmann constant. When further increasing the deposition rate with the deposition temperature set at a fixed value, that is, with the potential rate of surface reaction fixed, it is common to increase the actual surface reaction rate by increasing the source gas pressure P to increase the rate of transport in the gas phase. But, as mentioned previously, increasing the deposition rate by increasing the pressure unfortunately harms the film thickness uniformity. While this fact is recognized, the pressure inside the deposition chamber P is related to the pumping speed S and the gas flow rate Q by
P=Q/S.
Here there are three independent variables related by a single equation which results in the existence of two independent variables. In other words, if only pressure P is fixed, it is not possible to determine a single physical condition. This means that for an identical pressure of 100 mtorr, a system with a gas flow rate of 100 sccm and a pumping speed of 1 sccm/mtorr is completely different than a system with a gas flow rate of 1 sccm and a pumping speed of 0.01 sccm/mtorr. The inventor noticed this fact, and examined what kind of effect changes in the deposition chamber pumping speed and the disilane source gas flow rate had on the deposition rate and the film thickness uniformity while keeping the deposition temperature and deposition pressure constant. The results showed that even for a fixed deposition temperature and deposition pressure, the deposition rate increased along with increases in source gas flow rate; and further that the film thickness uniformity was improved. Additionally, this relationship was recognized to be strongly related to the total surface A inside the reaction chamber; and that it is necessary to increase the source gas flow rate in proportion to the total surface area. This will be explained using FIG. 5. Amorphous silicon films were deposited in a 184.5 l vertical, hot wall LPCVD reactor with thirty five 300 mmxc3x97300 mm substrates placed a distance of 10 mm apart. The total surface area of the 35 substrates was 63000 cm2 since the area of one substrate (front and back) is 30 cmxc3x9730 cmxc3x972 or 1800 cm2. Since the surface area of regions inside the reactor which can be coated with the semiconductor film during deposition is 25262 cm2, the total surface area which can be coated inside the reactor is
A=63000+25262=88262 cm2.
Under these conditions, semiconductor films were deposited by flowing only disilane into the deposition chamber at a deposition temperature of 425xc2x0 C. and a deposition pressure of 320 mtorr. The disilane flow rate was varied from 50 sccm to 400 sccm while the deposition pressure was kept constant at 320 mtorr by varying the deposition chamber pumping speed by means of the LPCVD reactor pressure control unit. The deposition rate as a function of disilane flow rate under the given conditions is shown by the circular data points and the xe2x80x9cDRxe2x80x9d solid line in FIG. 5 while the film thickness variation is shown by the square data points and the xe2x80x9cVxe2x80x9d dashed line. Since A is 88262 cm2, the corresponding R values for the given flow rates, Q, are: Q=50 sccm, R=5.66xc3x9710xe2x88x924 sccm/cm2; Q=100 sccm, R=1.13xc3x9710xe2x88x923 sccm/cm2; Q=200 sccm, R=2.27xc3x9710xe2x88x923 sccm/cm2; and Q=400 sccm, R=4.53xc3x9710xe2x88x923 sccm/cm2. For R greater than 2.27xc3x9710xe2x88x923 sccm/cm2, the deposition rate is essentially saturated; and the surface reaction rate and the potential rate of surface reaction nearly agree. As discussed previously, for a fixed deposition temperature and deposition pressure, a higher deposition rate is preferred from both the viewpoint of productivity and the viewpoint of semiconductor film quality. When the deposition rate is high, the film growth rate is large compared to the nucleation rate so that both the grain size in the films after crystallization increases and the amount of impurity gases from outgassing incorporated into the film is decreased. Both of these factors lead to improvement in the semiconductor film quality and mean increases in mobility and decreases in threshold voltage when these films are used as the active layer in thin film semiconductor devices.
Additionally, the decrease in impurity incorporation leads to suppression of the poly-Si TFT off current. On account of these factors, a high deposition rate is preferred, and as seen in FIG. 5, this value saturates for R greater than or equal to 2.27xc3x9710xe2x88x923 sccm/cm2. Consequently, a value of the higher silane flow rate per unit area of about 2.27xc3x9710xe2x88x923 sccm/cm2 or more is preferred for the deposition of semiconductor films. The present experiment was performed in a vertical reactor with the gas introduced from the top and exhausted from the bottom. Using R=5.66xc3x9710xe2x88x924 sccm/cm2 resulted in a difference in deposition rate of 18% between the upper most substrate and the lower most substrate. For R greater than or equal to about 1.13xc3x9710xe2x88x923 sccm/cm2, this difference was practically unobservable; and, therefore, to obtain uniformity among substrates, an R value greater than or equal to about 1.13xc3x9710xe2x88x923 sccm/cm2 is desirable. Further, as seen in FIG. 5, an Rxe2x89xa74.54xc3x9710xe2x88x923 sccm/cm2 is ideal since the variation within a single substrate is 5% or less and gives a high deposition rate of 1.30 nm/min.
The source gas flow rate which corresponds to the total surface area in the LPCVD reactor which can be covered with a semiconductor film must also be varied. In other words, the parameter which must be controlled is the higher silane flow rate per unit area, R. The exact same experiment described above was repeated with seventeen 235 mmxc3x97235 mm substrates placed a distance of 20 mm apart in the LPCVD reactor. The substrate area was 23.5 cmxc3x9723.5 cmxc3x972xc3x9717=18777 cm2. This was combined with the reactor area of 25262 cm2 to yield a total surface area of 44039 cm2. R values of about 5.66xc3x9710xe2x88x924 sccm/cm2, 1.13xc3x9710xe2x88x923 sccm/cm2, 2.27xc3x9710xe2x88x923 sccm/cm2, and 4.53xc3x9710xe2x88x923 sccm/cm2 correspond to higher silane flow rates of 25 sccm, 50 sccm, 100 sccm, and 199 sccm, respectively. When the deposition rate and film thickness uniformity among substrates was examined for the given disilane flow rates, behavior identical to that found previously was confirmed. That is, in addition to the deposition temperature and deposition pressure, the higher silane flow rate per unit area is a parameter necessary to unambiguously define the physical system. According to the discovery above, an R value of about 1.13xc3x9710xe2x88x923 sccm/cm2 or more is required for the deposition of a silicon-containing film at a deposition temperature of about 430xc2x0 C. or less and a disilane partial pressure of about 100 mtorr or more. For example, for the deposition of a semiconductor film using one hundred 400 mmxc3x97500 mm substrates set 15 mm apart in a 900 mm diameter cylindrical deposition chamber, the substrate surface area is 400000 cm2; and the surface area inside the deposition chamber is about 56550 cm2, leading to a total surface area A of about 456500 cm2. Therefore, the minimum necessary silane flow rate is given by the R value of 1.13xc3x9710xe2x88x922 sccm/cm2 multiplied by the area A or 518 sccm. Similarly, a minimum flow rate of about 1050 sccm is necessary for semiconductor film deposition in the case in which there are one hundred 560 mmxc3x97720 mm substrates placed 25 mm apart in a 1200 mm diameter chamber since A is approximately 919500 cm2 and Rxe2x89xa71.13xc3x9710xe2x88x923 sccm/cm2.
(2-5, Poly-Si TFT Channel Layer Thickness and Transistor Properties)
Here, the relationship between the semiconductor film thickness of the active layer forming the channel in a poly-Si TFT thin film semiconductor device and the transistor properties will be discussed. Generally, the optimum film thickness for the semiconductor film to be used as the channel in a thin film semiconductor device depends strongly on the fabrication method. This is because the film quality of the semiconductor film varies widely with the film thickness. For example, in systems such as SOS (silicon on sapphire) and SOI (silicon on insulator) in which the film quality does not, as a rule, depend on the film thickness, the transistor properties improve for thinner semiconductor films. (Here, this principle is called the thin film effect. ) This is because the inversion layer quickly spreads throughout the entire film thickness and the inversion layer can form readily in the case of thin semiconductor films (the threshold voltage Vth decreases). On the other hand, in thin film semiconductor devices using polycrystalline silicon films for the channel layer, the quality of the semiconductor film is vastly different depending on the film thickness; and the mechanism mentioned above is much more complicated. Usually, the film quality of polycrystalline films worsens as the film thickness decreases. Specifically, in comparison to thick films, the grain size in thin films is smaller; and the number of internal grain defects and grain boundary traps is simultaneously large. If the grain size is small, the mobility of thin film semiconductor devices using such films will be low. Additionally, if the number of internal grain defects and grain boundary traps is large, the spread of the depletion layer slows; and the threshold voltage Vth increases substantially. (Here, this principle is called thin film degradation.) Ultimately, the thin film effect mentioned earlier and thin film degradation are competing processes. If the films are made thin but there is little change in film quality (thin . film degradation is small), the thin film effect is applicable; and the transistor properties improve with thinner films. Conversely, if the films are made thin and there is a remarkable degradation of the film quality (thin film degradation is large), the thin film effect is canceled; and transistor properties worsen for thinner films. In other words, depending on the magnitude of the film quality dependence on the film thickness, the transistor properties may improve or may worsen with the use of thinner films. This dependence of film quality on film thickness differs depending on fabrication technique; and also differs depending on film thickness. Consequently, the optimum semiconductor film thickness is completely different depending on the fabrication process of the thin film semiconductor device; and the optimum thickness value must be determined for each fabrication process.
(2-6, Optimum Film Thickness for the LPCVDxe2x80x94Crystallization Method)
Here, the optimum poly-Si TFT semiconductor film thickness for a semiconductor film fabricated by first using LPCVD at a deposition temperature less than about 450xc2x0 C., ideally about 430xc2x0 C. or less, followed by crystallization for use in a low temperature process thin film semiconductor device of the present invention as described above is explained. Using LPCVD at less than about 450xc2x0 C., or less than or equal to about 430xc2x0 C., the deposited film can coalesce to form a continuous film when the film thickness reaches approximately 10 nm or more. If a continuous film does not form but only island regions exist, the semiconductor xe2x80x9conxe2x80x9d characteristics will be extremely poor because the film will still be discontinuous after crystallization regardless of the use of melt crystallization or solid phase crystallization. In short, thin film degradation has overwhelmingly defeated the thin film effect. Therefore, the minimum film thickness for LPCVDxe2x80x94crystallization is on the order of about 10 nm. As film thickness reaches about 20 nm or more, the transistor properties of melt crystallized films begin to improve. In the melt crystallization of semiconductor films, crystallization occurs with the is gathering of peripheral semiconductor atoms around a single central nucleus during the cooling solidification stage. Because of this, when film thickness is less than about 20 nm, even if a continuous film forms immediately after deposition by LPCVD, cracks and crevices are generated throughout the film following melt crystallization; and transistor properties still do not improve. In other words, in LPCVDxe2x80x94melt crystallization, thin film degradation dominates for films less than about 20 nm. As the film thickness reaches more than about 20 nm, thin film degradation gradually decreases; and the thin film effect begins to rival thin film degradation. Continuing the trend in increased film thickness, transistor properties are best for film thickness between about 20 nm and about 80 nm. For thicknesses greater than about 80 nm, the thin film effect predominates, and transistor properties deteriorate along with increases in film thickness. For semiconductor films about 30 nm or thicker, stable and reliable production is possible. Particularly with the advance of high precision processing, the problem of contact failure between the semiconductor film and the metallization can be decreased significantly for films approximately 30 nm or thicker when such processes as reactive ion etching (RIE) are used to open contact holes in the interlevel insulator layer or the gate insulator layer. Usually the combined thickness of the gate insulator layer and interlevel insulator layer is about 600 nm; and if the film thickness variation for this thickness is xc2x110%, or a total of 20%, the difference in film thickness between the thinnest insulator layer and the thickest insulator layer is on the order of 120 nm. Since the selectivity ratio of RIE with respect to semiconductor films is about 1:10, approximately 10-15 nm of the semiconductor layer lying beneath the thinnest insulator layer is removed during the opening of contact holes in the thickest insulator layer. Thus, even if about 15 nm is lost in such a manner during the opening of contact holes, the contact resistance is sufficiently low and the problem of contact failure does not occur if the semiconductor film thickness is about 30 nm or more. If the semiconductor film thickness is less than or equal to about 70 nm, the entire semiconductor layer can be uniformly heated and crystallization can proceed smoothly during melt crystallization using a laser or other means. If, however, the film thickness is greater than about 140 nm, only the upper portion of the layer is melted during laser irradiation from above and the bottom portion of the layer retains amorphous regions. This adds to the thin film effect and the transistor properties deteriorate profoundly. In other words, the maximum film thickness for the LPCVDxe2x80x94crystallization method is on the order of 140 nm.
(2-7, Semiconductor Film Deposition Using the PECVD Process of this Invention)
The method of forming the semiconductor film of the thin film semiconductor device of this invention using the PECVD process will be described. The PECVD reactor used here is the capacitively-coupled type. The plasma uses industrial frequency rf waves (13.56 MHz) and is generated between two parallel plate electrodes. Of the two parallel plate electrodes, the lower parallel plate electrode has ground electrical potential. The substrate on which the semiconductor film is to be deposited is placed on this electrode. The rf waves are supplied to the upper parallel plate electrode. In addition, multiple gas introduction ports exist in the upper parallel plate electrode, and the source gases are supplied in a uniform laminar flow from this electrode to the deposition chamber. The pressure at the time the film formation takes place is from approximately 0.1 torr to approximately 5 torr. The distance between the parallel plate electrodes can be varied from about 10 mm to about 50 mm.
After forming the underlevel protection layer on at least a portion of the substrate surface using an insulating material, such as a silicon oxide film, a semiconductor film is formed on top of this underlevel protection layer. Ultimately, a thin film semiconductor device that uses the semiconductor film as the transistor""s active layer will be produced. When a semiconductor film is to be deposited using the PECVD process, initially the underlevel protection layer is exposed to an oxygen plasma after the substrate has been placed in the deposition chamber of the PECVD reactor. The oxygen plasma is generated at an electrode spacing of about 15 mm to 35 mm, a pressure of about 1.0 torr to 2.0 torr and an rf power density of approximately 0.05 w/cm2 to 1 w/cm2. The temperature of the substrate is the same 250xc2x0 C. to 350xc2x0 C. as that during semiconductor deposition, and the oxygen plasma exposure time is from about 10 seconds to one minute. After exposure to the oxygen plasma, the plasma is temporarily stopped and the deposition chamber is pumped down for 10 seconds to 30 seconds. If the vacuum pump-down takes place for 15 seconds or more, the level of the vacuum in the deposition chamber will be 1 mtorr or lower. This takes place to prevent oxygen from being incorporated into the semiconductor film during semiconductor film deposition in the subsequent process step. After pulling the vacuum, the source gases that are used for semiconductor film deposition, such as silane and hydrogen, are allowed to flow for 10 seconds to two minutes without generating a plasma. During this time, the conditions inside the deposition chamber, such as the pressure and source gas flow rate, are the same as those used during semiconductor film deposition. Because this will result in the oxygen in the deposition chamber being entirely replaced by the source gas, the incorporation of oxygen into the semiconductor film will be minimized. Further, if the period of gas flow is 30 seconds or more, the temperature of the substrate is maintained at a constant temperature, and the semiconductor film can always be deposited under the same conditions. In the thin film semiconductor device of this invention, the upper-most layer of the underlevel protection layer is composed of a film such a silicon oxide, which has a low nucleation rate. Since this silicon oxide film is formed using the CVD process or the PVD process, there will always be dangling bonds of the silicon. For this reason, if the semiconductor film is formed on top of the underlevel protection layer without some kind of pre-treatment, the dangling bonds would act as fixed electrical charges within the underlevel protection layer. As previously stated, when the semiconductor film is thin, at or below a few hundred nanometers, these fixed electrical charges will cause negative influences on the thin film semiconductor device, such as causing variations in the threshold voltage (Vth). By applying an oxygen plasma to the surface of the underlevel protection layer, the dangling bonds will bind with the oxygen atoms, and thus drastically reduce the fixed electrical charges within the underlevel protection layer. In other words, even though the semiconductor film is made thin enough to improve the semiconductor properties, instabilities in the properties, such as the Vth fluctuations caused by the underlevel protection layer, can be resolved. Moreover, the exposure to oxygen plasma will clean the surface of the underlevel protection layer through the oxidation reaction (combustion) and restrain even further the nuclei generation rate at the initial stage of semiconductor deposition. This will increase the purity of the semiconductor film, enlarge the areas that form the deposited film, and enlarge the crystal grains that form the crystallized semiconductor film. In terms of the properties of the thin film semiconductor device, this is manifest as a decrease in the off current, a reduction in Vth, an improvement in the switching properties because sub- threshold swing will steepen, and an increase in the mobility.
To improve the underlevel protection layer surface, in addition to exposure to an oxygen plasma, exposure to a hydrogen plasma is also effective. That is, after the substrate on which the semiconductor film is to be deposited is placed inside the PECVD reactor, the underlevel protection layer on the substrate is first exposed to a hydrogen plasma. Then, without breaking vacuum, the semiconductor film is sequentially formed on top of the underlevel protection layer. The semiconductor deposition conditions use a lot of hydrogen, as in hydrogen 3000 sccm and monosilane 100 sccm. Furthermore, when the ratio of hydrogen is 10 times or more that of silane, it is also possible to have continuous processing, from hydrogen plasma processing to semiconductor film formation, without stopping the plasma. When the semiconductor film deposition conditions differ from the hydrogen plasma conditions, as with monosilane 100 sccm in argon 7000 sccm, the plasma is temporarily terminated after the hydrogen plasma processing; and, except for the fact that the plasma is not generated, it is desirable to have all other process parameters the same as for the semiconductor film deposition conditions in order to create a stabilization period before the deposition. Doing so will allow the substrate temperature to always be constant when the semiconductor film is deposited. The hydrogen plasma processing time is from 10 seconds to one minute, and the stabilization period before the semiconductor film deposition is from 10 seconds to two minutes.
Of the dangling bonds in the underlevel protection layer, there are those that are terminated by oxygen, as in Sixe2x80x94*, and those that cannot be terminated by oxygen, as in Sixe2x80x94Oxe2x80x94*. Because hydrogen plasma exposure can terminate these dangling bonds in the form of Sixe2x80x94H and Sixe2x80x94OH, an extraordinary effect can be observed in the decrease in the fixed electrical charges in the underlevel protection layer. In addition, because hydrogen plasma processing also has the effect of etching and cleaning the underlevel protection layer surface, it also increases the purity of the semiconductor film. Further, the adhesion of the underlevel protection layer and the semiconductor film improves dramatically as a result of this cleaning. When a semiconductor film is formed using the PECVD process, crater-shaped holes can be generated in the semiconductor film; and the film sometimes peels off depending on the deposition conditions. This can be prevented, however, by processing with hydrogen plasma.
When a semiconductor film is deposited, it is even more desirable to process with both oxygen plasma and hydrogen plasma. In other words, initially expose the surface of the silicon oxide underlevel protection layer to an oxygen plasma. At first, dangling bonds in the underlevel protection layer will be terminated by the oxidation reaction. At the same time, the surface will be cleaned by means of combustion, and this will suppress the rate of nuclei generation. Next, the oxygen plasma is terminated, and a vacuum is pulled for a period of from about 10 seconds to one minute to remove the oxygen within the deposition chamber. The underlevel protection layer is then sequentially exposed to a hydrogen plasma without breaking vacuum. Some dangling bonds that could not be terminated with the oxygen plasma will be terminated with the hydrogen plasma, and this will reduce the fixed electrical charges in the underlevel protection layer to a minimum. Moreover, the surface will become even cleaner and at the same time the adhesion between the semiconductor film and the underlevel protection layer will also improve. After processing with the hydrogen plasma, vacuum pump-down and substrate heating will take place as needed; and the semiconductor film is formed on the underlevel protection layer sequentially without breaking vacuum. Doing this will not only bring about both the previously mentioned oxygen plasma effect and hydrogen plasma effect, but there will also be a clear reduction in the amount of oxygen incorporation into the semiconductor film since the hydrogen plasma step comes between the oxygen plasma step and the formation of the semiconductor film. This will also allow a higher purity and higher quality semiconductor film to be obtained. As stated in section (2-1), for a melt crystallized semiconductor film, a clean underlevel protection layer surface and control of the underlevel protection layerxe2x80x94semiconductor interface are particularly important. Consequently, the underlevel protection layer surface processing prior to semiconductor film deposition is exceptionally significant.
Next, the processing after the semiconductor film has been formed using the PECVD process will be described. After the semiconductor film has been formed on top of the underlevel protection layer, it is desirable to sequentially expose the semiconductor film to a plasma without breaking vacuum. This will terminate the dangling bonds of the semiconductor atoms, such as those of silicon. This is particularly effective when the film is formed under conditions in which there is little hydrogen when the semiconductor film is deposited. For example, it is particularly effective in a system in which the amount of hydrogen is less than 50 percent of the gases that are introduced to the deposition chamber, such as when the semiconductor film is deposited using silane mixed with inert gases such as helium or argon. When a semiconductor film is deposited using such a system, a huge number of dangling bonds will exist in the film. Since these dangling bonds are extremely chemically active, they will react with a variety of impurities and substances that exist within the atmosphere, or these materials can physically adsorb. If crystallization takes place in such a condition using a laser, for example, the purity of the semiconductor will decrease. In addition, the grains will become smaller since the adsorbed substances become the nuclei for crystal growth. Such problem points can be easily eliminated by hydrogen plasma processing. In other words, a high purity, high-quality semiconductor film is in and of itself unstable and can be contaminated by the atmosphere. Such a high purity, high-quality film, however, can be stabilized by applying a hydrogen plasma after the film has been formed.
After the semiconductor film has been formed on top of the underlevel protection layer, the same type of effect can also be accomplished by sequentially exposing the semiconductor film to an oxygen plasma without breaking vacuum. When the semiconductor film is silicon or when silicon is the main component, oxygen plasma will form a silicon oxide film on the semiconductor film surface. This oxide film is extremely stable. Compared to the semiconductor film surface, its ability to prevent chemical and physical contaminant adsorption as well as diffusion of such contaminants to the semiconductor film is excellent. That is, it is optimal for protecting the semiconductor film from external contaminants. Further, because the oxidation takes place using an oxygen plasma in which the oxygen is quality-adjusted for high purity as opposed to oxygen in the atmosphere, the purity of the oxide film itself is high. During subsequent crystallization, it is desirable to remove the oxide film. Yet, even if the oxide film is not removed, there are virtually no problems with contaminants from the oxide film being incorporated into the semiconductor film.
Ideally, after the semiconductor film has been deposited using a PECVD reactor, the film is exposed to a hydrogen plasma sequentially without breaking vacuum, and this will inactivate most of the dangling bonds by hydrogen termination. Subsequent to this and again sequentially without breaking vacuum, the semiconductor film is exposed to an oxygen plasma. This oxygen plasma will terminate any dangling bonds that were not terminated by the hydrogen plasma and can also be expected to form on the surface of the semiconductor film a highly pure silicon oxide film that protects the semiconductor film from external contamination. Using this method of processing, not only will both the hydrogen plasma effect and the oxygen plasma effect be obtained, but also the effect of the dangling bond termination will increase and the amount of oxygen incorporated into the semiconductor film can be reduced. As a result, the semiconductor film purity after the crystallization will increase more so than processing with the oxygen plasma alone, forming a better thin film semiconductor device.
In the oxygen plasma exposure stage, as stated previously, regardless of the LPCVD and PECVD processes and even if the greatest amount of care is taken so that the semiconductor film becomes very pure, because an oxide film exists on the surface of the semiconductor film, the quality of the crystallized film will decrease if oxygen is incorporated into the semiconductor film during crystallization. This situation becomes particularly serious in the case of melt crystallization such as by laser irradiation.
A semiconductor film which has been carefully prepared using underlevel protection layer surface preparation and the LPCVD and PECVD processes, as in this invention, requires that the same type of care be taken when crystallizing. In other words, when a semiconductor film that forms the active layer of a thin film semiconductor device is formed by melt crystallization, such as by laser irradiation, it is desirable to remove the oxide film from the semiconductor film surface immediately prior to melt crystallization. Doing so will allow the amount of oxygen from the oxide layer that gets into the semiconductor film to be reduced to a minimum when semiconductor film melting occurs. If the amount of oxygen that gets into the semiconductor film is reduced, not only will the crystallinity of the crystallized film increase, the defect density will decrease and the transistor properties will greatly improve.
The processing method that makes the removal of the oxide film immediately prior to crystallization the easiest is one that uses a hydrofluoric acid solvent. Of course, the oxide film can be removed by a gas-phase plasma process such as by using an NF3 plasma. It is desirable to crystallize the semiconductor film immediately after removing the oxide film. If the semiconductor film is melt crystallized within two hours of the completion of the oxide film removal process, the amount of oxygen that gets into the semiconductor film will be extremely low.
(2-8, Melt Crystallization of a Mixed-Crystallinity Semiconductor Film)
The thin film semiconductor device of this invention is most effective for top-gate poly-Si TFTs which are produced at temperatures of 350xc2x0 C. or lower for all process steps from the formation of the gate insulator layer forward. As a consequence, if the semiconductor film formation step can take place at a temperature of 350xc2x0 C. or lower, all of the process steps will take place at 350xc2x0 C. or lower. Currently, the thickness of the conventional glass substrates for LCDs is 1.1 mm. If this were 0.7 mm, however, not only would the glass substrates become cheaper, but also major benefits in the portability and the production of the LCDs would arise because of the lighter-weight substrate. Since the density of glass is approximately 2.5 g/cm3, the weight of one sheet of glass with dimensions of 400 mmxc3x97500 mmxc3x97xe2x88x921.1 mm, for example, is about 550 grams. If such glass substrates were processed in batches of 100 sheets, the weight would be 55 kg, which would be a large load for production equipment and for transport robots. It goes without saying that if the thickness were 0.7 mm, the weight of a batch would decrease to 35 kg, significantly reducing the load. For this reason, thinning of the glass substrates is desirable. Such a large thin film glass would bow significantly under its own weight, however, even at room temperature as shown in FIG. 4. And no matter what method were used with the LPCVD process, a semiconductor film could not be formed. In other words, in order to use such a large piece of thin glass, the semiconductor film would have to be formed using the PECVD process at a temperature of 350 degrees C or lower. Yet, in general, because of low density of the films and the large amount of incorporated hydrogen, an amorphous semiconductor film formed using the PECVD process cannot crystallize unless it first undergoes thermal annealing at 450xc2x0 C.
When the inventor conducted various studies of semiconductor films from the PECVD process, it was discovered that when using the PECVD process at a deposition rate of about 0.1 nm/s or higher, a mixed-crystallinity semiconductor film was produced and when this mixed-crystallinity semiconductor film was exposed to laser light, melt crystallization was possible even without the thermal annealing step mentioned above. Although the existence of crystal structure in this mixed-crystallinity film can barely be observed by Raman spectrometry, for instance, it is difficult to call the film polycrystalline. In addition, the density is as low as the amorphous silicon formed using the PECVD process of the prior art, and hydrogen atoms are contained at just under 20 percent of the silicon atoms. The details of why such a film can be melt crystallized in an orderly manner are not known. But it is believed that it might be that the amorphous region is more easily melted than the microcrystalline region, and that the microcrystals that float in the melted silicon liquid play the role of restricting the evaporation and the scattering of the melted silicon liquid. Yet, even for a mixed-crystallinity semiconductor film, it is difficult to melt crystallize such a film with a deposition rate of about 0.1 nm/s or lower. As in the case with LPCVD in which it seems that film quality decreases for slower deposition rates as a result of the increased ease of impurity incorporation, the incorporation of impurities during film growth in PECVD also seems to be the main factor leading to difficulties in crystallization. In contrast to a background vacuum pressure in the 10xe2x88x927 torr range using LPCVD reactors, the background vacuum pressure is in the 10xe2x88x924 torr range in PECVD reactors, and this may be the reason that high-speed film deposition can be observed using PECVD. In addition, if the deposition rate was 0.37 nm per second or higher, there was an improvement in the adhesion between the semiconductor film and the underlevel protection layer; and the generation of crater-shaped holes and film peeling virtually disappeared. Using the PECVD process, a mixed-crystallinity silicon film can be obtained by setting the ratio of the hydrogen to monosilane flow rates to approximately 30:1. Alternatively, ac mixed-crystallinity silicon film can be obtained by setting the ratio of the flow rates of inert gases like argon to that of the chemical specie containing the constitutive elements of the semiconductor film, such as monosilane, to less than about 33:1 (less than about 3 percent monosilane concentration). Based on experiments by the inventor, hydrogen-monosilane system mixed-crystallinity can also be melt crystallized without thermal annealing. The laser energy range in which melt crystallization proceeds well, however, is limited to several tens of mJ/cm2. In contrast to this, an argon-monosilane system mixed-crystallinity silicon film will crystallize smoothly in a wide laser energy region, from 100 mJ/cm2 to 350 mJ/cm2. Therefore, an argon-monosilane system mixed-crystallinity silicon film is more suitable as the semiconductor film of low temperature process poly-Si TFTs. The optimal argon to monosilane flow ratio for melt crystallization is from about 124:1 (approximately 0.8 percent monosilane concentration) to about 40.67:1 (approximately 2.4 percent monosilane concentration).
(2-9, Optimum Film Thickness of PECVDxe2x80x94Crystallized Films)
Here, the optimum semiconductor film thickness for a poly-Si TFT, of a low temperature process thin film semiconductor device of the present invention described above, that was fabricated through crystallization after the semiconductor film was formed using the PECVD process at a deposition temperature of 350xc2x0 C. or lower will be described. Among the low temperature process thin film semiconductor devices of this invention that have been discussed above, here will be described. In the PECVD process, as in the LPCVD process, a film will become continuous when it reaches a thickness of 10 nm or more. However, the density of the semiconductor film obtained using the PECVD process is from approximately 85% to 95% of the film density obtained using the LPCVD process. For this reason, if the 10 nm semiconductor film of the PECVD process is crystallized, its film thickness will fall to about 9 nm after crystallization. Thus, the minimum film thickness of a PECVDxe2x80x94crystallized film will be approximately 9 nm. As with LPCVD-crystallized films, if the film thickness is about 18 nm or more, the transistor properties of the melt crystallized film will begin to improve. That is, with PECVD-melt crystallization, at 18 nm or less, thin film degradation is dominant; and, at 18 nm or higher, thin film degradation decreases, and the thin film effect becomes competitive. This will continue if the film thickness is between approximately 18 nm and approximately 72 nm and the transistor properties are optimum for films within this thickness range. If the film is thicker than 72 nm, the thin film effect takes control and the transistor properties will gradually deteriorate as the thickness of the film increases. If the semiconductor film thickness is 30 nm or more, it is possible to have stable production of highly integrated thin film semiconductor devices that require fine geometry fabrication. In other words, with RIE, contacts holes can be opened up reliably without the appearance of contact failure. If the semiconductor film thickness immediately after deposition using the PECVD process is about 80 nm or less, the entire semiconductor layer can be uniformly heated and crystallization can proceed smoothly during melt crystallization using a laser or other means. After crystallization, the thickness of the film will be approximately 72 nm. If the semiconductor film immediately after deposition is about 150 nm thick or higher, only the upper portion of the layer is melted during laser irradiation from above and the bottom portion of the layer retains amorphous regions. This adds to the thin film effect and the transistor properties deteriorate profoundly. In other words, the maximum film thickness for the PECVDxe2x80x94crystallization method is on the order of about 135 nm after crystallization.
(2-10, MOS Interface, the Gate Insulator Layer and the Thermal Environment)
With this invention, the gate insulator layer is formed using CVD or PVD after the semiconductor film crystallization is finished. No matter what process is used to form the gate insulator layer, it is desirable that the insulator layer formation temperature be at 350xc2x0 C. or lower. This is because it is important to prevent the thermal degradation of the MOS interface and the gate insulator layer. This same thing applies to all of the subsequent process steps. All of the process steps after forming the gate insulator layer have to be held to 350xc2x0 C. or less. In general, a gate insulator layer formed using CVD or PVD has many dangling bonds within the film; and the structure of the film is also unstable. This invention terminates the dangling bonds by exposure to oxygen plasma. In addition, CVD silicon oxide films contain Sixe2x80x94OH groups. Dangling bonds that have been terminated by such hydroxyl groups and oxygen plasmas are unstable in heat, easily dissociating in an environment of 350xc2x0 C. or higher. That is, dangling bonds such as Sixe2x80x94Oxe2x80x94* and Sixe2x80x94* are generated again at the MOS interface and in the gate insulator layer. These become interface states or fixed charges in the insulator layer and cause a deterioration of the transistor properties. In the prior art, hydrogen plasma processing took place for an hour in order to overcome this. In this invention, however, because all of the process steps after the semiconductor film has been formed take place at 350xc2x0 C. or less, such thermal degradation does not occur. For this reason, hydrogenation is not required. With this invention, a high performance, thin film semiconductor device can be produced easily and reliably. Although it is to be expected, the thermal degradation extends to the underlevel protection layer as well. As described in section (2-1), thermal degradation of the underlevel protection layer will lead to the deterioration of the properties of the thin film semiconductor device. Although it is not as sensitive as the gate insulator layer, the influence is such that it cannot be ignored. For this reason, optimization of the thin film semiconductor device is achieved, theoretically, by having all processing steps, including the semiconductor film deposition steps, take place at a temperature of 350xc2x0 C. or lower. Doing so will avoid thermal degradation of both the underlevel protection layer and the gate insulator layer. Processes that can form semiconductor films at temperatures of 350xc2x0 C. or lower include PECVD and sputtering.
(2-11. The VHF-PECVD Reactor Used in this Inventions
First of all, FIG. 2 will be used to describe the general configuration of the VHF-plasma enhanced chemical vapor deposition reactor (VHF-PECVD reactor) used in this invention. The PECVD reactor is a capacitively-coupled type, and the plasma is generated between parallel plate electrodes using a 144 MHz VHF power supply. The top drawing in FIG. 2 is an overall perspective of the reaction chamber as viewed from above, a drawing of cross section A-Axe2x80x2 is shown in the bottom of FIG. 2. Reaction chamber 201 is isolated from the outside by reaction vessel 202, which is in a reduced pressure condition of from about 5 mtorr to 5 torr during film formation. Inside of reaction vessel 202, lower plate electrode 203 and upper plate electrode 204 are placed in mutually parallel positions. These two electrodes form the parallel plate electrodes. The space between these parallel plate electrodes is reaction chamber 201. This invention uses parallel plate electrodes with dimension of 410 mmxc3x97510 mm. Since the distance between the electrodes is variable from 10 mm to 50 mm, the volume of reaction chamber 201 varies from 2091 cm3 to 10455 cm3, depending on the distance between the electrodes. The distance between the parallel plate electrodes can be set freely between 10 mm and 50 mm, as stated above, by moving the position of lower electrode 203 up and down. Moreover, when set to a designated electrode distance, the deviation of the electrode distance over the 410 mmxc3x97510 mm plate electrode surfaces is a mere 0.5 mm. As a result, the deviation in the electrical field strength that appears between the electrodes is 5.0% or less over the plate electrode surfaces; and an extremely uniform plasma is generated within reaction chamber 201. Substrate 205 on which thin film deposition is to take place is placed on top of lower plate electrode 203 and 2 mm of the substrate edge is held down by shadow frame 206. Shadow frame 206 has been omitted from the upper drawing of FIG. 2 to make the overall drawing of the PECVD reactor easy to understand. Heater 207 is installed within lower plate electrode 203. The temperature of lower plate electrode 203 can be adjusted as desired from 25xc2x0 C. to 400xc2x0 C. Except for the peripheral 5 mm, the temperature distribution within lower plate electrode 203 is within xc2x11.0xc2x0 C. relative to the set-point temperature. Essentially, even if the size of substrate 205 were 400 mmxc3x97500 mm, the temperature deviation within the substrate could be maintained to within 2.0xc2x0 C. For example, if a conventional glass substrate (such as Corning Japan""s #7059, Nippon Electric Glass Co., Ltd.""s OA-2, or NH Techno Glass""s NA35) were used as substrate 205, shadow frame 206 would hold substrate 205 down to prevent it from deforming concavely by the heat from heater 207 as well as to prevent unnecessary thin films from being formed on the edges and back surface of the substrate. The reaction gas, which is made up of source gases and additional gases as required, flows through tube 208 and is introduced into upper plate electrode 204. It then flows between gas diffusion plates 209 located inside upper plate electrode 204, and flows from the entire surface of the upper plate electrode into reaction chamber 201 at a virtually uniform pressure. If film formation is taking place, some of the reaction gas will be ionized when it exits the upper plate electrode and cause a plasma to be generated between the parallel plate electrodes. From a part to all of the reaction gas will participate in film formation. Residual reaction gas that has not participated in film formation and gases formed as a result of the film forming chemical reaction will become discharge gases and be discharged through exhaust port 210 which is in the top of the peripheral section of reaction vessel 202. The conductance of discharge port 210 is sufficiently large compared to the conductance between the parallel plate electrodes. The desired value is one that is 100 times or more of the conductance between the parallel plate electrodes. In addition, the conductance between the parallel plate electrodes is even sufficiently larger than the conductance of gas diffusion plate 209, and that desired value is also 100 times or more of the conductance of gas diffusion plate 209. Through such a configuration, reaction gas can flow into the reaction chamber virtually uniformly from the entire surface of the large 410 mmxc3x97510 mm upper plate electrode; and, at the same time, discharge gas will be discharged in all directions from the reaction chamber in an even flow. The flow rates of the various reaction gases to tube 208 will be adjusted to their designated values by mass flow controllers. In addition, the pressure within reaction vessel 202 will be adjusted to the desired value by conductance valve 211, which is located at the exit of the discharge port. A pumping system, such as a turbomolecular pump, is located on the exhaust side of conductance valve 211. In this invention, an oil-free magnetic levitation type turbomolecular pump is used as part of the pumping system, and the background vacuum within reaction vessels such as the reaction chamber is set to the 10xe2x88x927 torr level. In FIG. 2, arrows are used to show the general flow of the gas. Both reaction vessel 202 and lower plate electrode 203 are at ground potential. These and upper plate electrode 204 are electrically isolated by insulation link 212. When a plasma is generated, for example, 144 MHz VHF waves that are generated from VHF wave oscillation source 213 are amplified by amplifier 214, pass through matching circuit 215, and are applied to upper plate electrode 204.
As stated above, because the PECVD reactor used in this invention has very sophisticated intra-electrode interval control and uniform gas flow, it is a thin film formation reactor that is able to handle large substrates of 400 mmxc3x97500 mm in size. However, by merely adhering to these basic concepts, it can easily handle further enlargements in the substrate. Actually, it is possible to produce a reactor that can handle even larger substrates of 550 mmxc3x97650 mm. In addition, in this invention, a common 144 MHz VHF wave frequency was used. Of course, VHS waves using other frequencies may also be used. For example, VHF waves from 100 MHz to 1 GHz may all be used. On the other hand, if the rf frequency is from 10 MHz to several hundred MHz (VHF), it is possible to generate a plasma between the parallel plate electrodes. Therefore, frequencies such as 27.12 MHz, 40.68 MHz, 54.24 MHz and 67.8 MHz, which are whole number multiples of the industrial rf frequency (13.56 MHz) may be used. In other words, by changing VHF wave oscillator 213, amplifier 214, and matching circuit 215 of the PECVD reactor used in this invention, a plasma using electromagnetic waves of a desired frequency can be easily generated. In general, in the case of an electromagnetic wave plasma, if the frequency is increased, the electron temperature within the plasma will increase and radicals can be easily created. For this reason, as will be explained later, even if the temperature of the substrate is as low as approximately 340xc2x0 C., the deposited film will already be in a polycrystalline silicon condition immediately after deposition. Thus, poly-Si TFTs can be easily fabricated even without special crystallization process steps.
(2-12, Semiconductor Film Formation and the Gases Used for Formation When Using VHF-PECVD and Microwave PECVD)
One of the characteristics of this invention is that a film deposited by VHF-PECVD or microwave PECVD is polycrystalline immediately after deposition (an as-deposited film). It is extremely difficult to make a polycrystalline as-deposited film using normal PECVD processing. Since the substrate temperature is less than 400xc2x0 C., the mobility of source materials such as silane on the surface of the growing film decreases; and the selectivity of the source material for the polycrystalline state as opposed to the amorphous state is lost. This invention eliminates this deficiency in the PECVD method by diluting source materials using noble gas elements and by using a VHF plasma or microwave plasma, both of which are capable of raising the electron temperature. To form a polycrystalline film in the as-deposited state, radicals and ions of the noble gas elements, such as helium (He), neon (Ne), and argon (Ar), are generated, without generating radicals and ions of the source materials, and must carry energy to the surface of the substrate. Because radicals and ions of source materials cause vapor phase reactions or react the instant they arrive at the substrate surface, selectivity is lost, thereby preventing polycrystalline growth. For these reasons, the generation of such radicals and ions within a plasma must be avoided at all costs. The source materials are carried to the surface of the growing film in an inactive state and become adsorbed there. Subsequently, if energy for reaction is supplied, such as by a dilute gas, a polycrystalline film will be formed in the as-deposited state. Consequently, dilution of the source gas is desired, and this gives rise to the necessity of selecting as the dilution gas a gas that promotes reaction of the source materials on the substrate surface. It goes without saying that the noble gas elements are composed of individual atoms, and, for this reason the ionization potential spectrum is very simple. For example, the monovalent ionization potential of helium is 24.587 eV, while the divalent ionization potential is only 54.416 eV. Further, the monovalent ionization potential of neon is 21.564 eV, while the divalent ionization potential is 40.962 eV. The monovalent ionization potential of argon is 15.759 eV, while the divalent ionization potential is 27.629 eV, and the trivalent ionization potential is 40.74 eV. Therefore, when a small amount-of source materials is diluted in helium and a plasma is generated, most of the ionized helium will be 24.587 eV monovalent ions. When a small amount of source materials are diluted in neon and a plasma is generated, the neon will be ionized into mainly monovalent ions of 21 564 eV. For argon, although both the monovalent ions and divalent ions are dominant, argon radicals and ions are effectively generated even when the source material is not diluted by a large amount of argon because the ionization energy is relatively low. In contrast to this, there is hydrogen, widely used as a dilution gas in the prior art, in which more than ten different ionization potentials exist between 15 eV and 18 eV for the ionization potential of the hydrogen molecules. For this reason, in contrast to noble gas elements such as helium which form plasmas containing one or two energies (laser light if referred to in terms of light), molecular gases such as hydrogen form plasmas containing a mixture of energies (white light if referred to in terms of light). Just as laser light will transport energy more effectively than white light, energy is transported to the substrate surface more effectively when the source gas is diluted by a noble gas element. In addition to the noble gas elements of helium, neon and argon, krypton (Kr) and xenon (Xe) may of course also be used as dilution materials during the deposition of semiconductor films. On the other hand, since VHF and microwave plasmas have high average electron temperatures within the plasma, the radical generation efficiency can be increased at relatively low power. In other words, since high power is not necessary, these plasmas generate few high energy ions, and resulting film damage is kept to a minimum. Further, a high radical generation efficiency also increases the film growth rate. If this invention were also carried out using the 13.56 MHz rf plasma used widely in the prior art, the film formation rate would be extremely slow, less than several xc3x85/min, making it absolutely unsuitable for utilization. Moreover, a very slow film formation rate will be harmful, reducing the quality of the film. Which is to say that it is precisely because VHF plasmas and microwave plasmas are used that this invention can be attained. In this sense, this invention can be very easily achieved by also using microwave PECVD, having a frequency an integer multiple of 2.45 GHz. And with such systems, there is an even greater degree of freedom in film formation conditions than in VHF-PECVD, meaning a semiconductor film with even better crystallinity can be deposited with greater ease.
(2-13, Optimum Film Thicknesses for VHF-PECVD and Microwave PECVD As-Deposited Films)
When placing a film in the polycrystalline state immediately after deposition (as-deposited) using VHF-PECVD or microwave PECVD, the film quality for film thicknesses ranging from 0 to 500 xc3x85 will be extremely poor compared to normal crystallized films. The film will consist of small, island-shaped crystalline grains in a sea of amorphous material, have a very low degree of crystallinity, and contain a large number of defects. From 500 xc3x85 to 1000 xc3x85, the ratio of crystal grains to the amorphous material will increase. From about 1000 xc3x85 to 1500 xc3x85, the semiconductor surface will be generally covered with crystal grains; and the amorphous components on the surface will almost disappear. From about 1500 xc3x85 to 2000 xc3x85, the size of the crystal grains will gradually increase along with the film thickness. At 2000 xc3x85 or higher, the film will grow while the crystal grains maintain approximately the same shape. The film thickness dependency of the transistor properties will also change in response to changes in the film quality relative to the film thickness. At 2000 xc3x85 or higher, because the film quality will exhibit virtually no change (because there is almost no thin film degradation), the thin film effect is active; and the thinner the film, the better the transistor properties become. At film thicknesses of 2000 xc3x85 to 1500 xc3x85, thin film degradation will begin to take effect. Yet; as before, the thin film effect will remain dominant. Although this will be more lax than at 2000 xc3x85 or higher, even here, the thinner the film the better the transistor properties become. Between 1500 xc3x85 and 200 xc3x85, thin film degradation and the thin film effect become competitive and transistor properties in the on condition reach their maximum values. With a film thickness of less than 200 xc3x85, thin film degradation overcomes the thin film effect, and the thinner the film, the poorer the transistor properties. Put another way, in the case of this invention, transistor properties are the best at semiconductor film thicknesses from 200 xc3x85 to 1500 xc3x85, but ideally between 400 xc3x85 to 1300 xc3x85. Until this point, the discussion has been about transistor properties in the on state; but the leak current will also vary with the thickness of the film. The principles of off state leakage in thin film semiconductor device are not well understood. In this invention, the principles are unclear; but, if the film thickness is 1000 xc3x85 or more, there is a strong positive correlation between the film thickness and off state leakage. The thicker the film, the larger the off state leakage. If the film thickness is less than 1000 xc3x85, the correlation weakens and becomes independent of the off state leakage. In other words, between 0 and 1000 xc3x85, the off state leakage current is almost consistently at a minimum. Consequently, the on state transistor properties are best, and the film thicknesses in which the off state leakage is the smallest are from 200 xc3x85 to 1000 xc3x85, but ideally from 400 xc3x85 to 1000 xc3x85. When the thin film semiconductor device of this invention is used in an LCD, it is desirable to consider the effects of light exposure on the off state leakage current. Light exposure will cause an increase in the off state leakage current in thin film semiconductor devices. This is called the optical leakage current. Having a sufficiently small optical leakage current is a condition for a good thin film semiconductor device. In the case of the thin film semiconductor device of this invention, the optical leakage current is proportional to the film thickness. From the perspective of reliable production and optical leakage current coexisting, it is desirable to have a film thickness from about 100 xc3x85 to 800 xc3x85. In a case in which the off state leakage and optical leakage are important, such as when using a thin film semiconductor device for the pixel switching element of an LCD, it is desirable to have a semiconductor film thickness from 100 xc3x85 to 700 xc3x85. Moreover, when it is necessary to give even stronger consideration to on current, the optimum thickness is from 200 xc3x85 to 800 xc3x85. A system that would satisfy all conditions would have a thickness from 400 xc3x85 to 800 xc3x85, but ideally from 600 xc3x85 to 800 xc3x85. Further, it is normally quite difficult to activate implanted ions in the source and drain regions at a low temperature of 350xc2x0 C. or lower as happens with this invention. This is the reason that to carry out activation in a stable manner, a lower limit must be set for the semiconductor film thickness. With this invention, the desired value is 300 xc3x85 or higher. If an LDD structure is to be utilized, a thickness of 500 xc3x85 or higher is desired.
(2-14, Crystallization of the Semiconductor Film through VHF-PECVD and Microwave PECVD)
As described in detail in section (2-12), although a polycrystalline film in the as-deposited state can be obtained easily using VHF- PECVD, the film quality is not as good as a crystallization film. On the other hand, it is difficult to crystallize a film obtained from the normal PECVD process as long as it has not been dehydrogenated or carefully annealed. In contrast, a semiconductor film from VHF-PECVD or microwave PECVD can be very easily crystallized using RTA or VST-SPC, or be melt crystallized such as by laser irradiation. Since most of the film will already be in an as-deposited crystalline state and residual amorphous components will be limited, crystallization of residual amorphous components can be achieved by means of a relatively low energy supply. Also, even when melt crystallization progresses using high energy, the polycrystalline components play the role of preventing the evaporation and scattering of semiconductor atoms. Thus, crystallization can proceed smoothly without semiconductor film damage, surface roughness, material loss and other problems. Ultimately, it can be said that rather than having a film obtained through the VHF-PECVD process or the microwave PECVD process as the active area of a thin film semiconductor device in the as-deposited state, it is more suitable to have such a film be the first semiconductor layer when producing low temperature poly-Si TFTs in which the highest temperature of the process step is 350xc2x0 C. or lower using melt crystallization. Put differently, a high-performance thin film semiconductor device can be produced by forming a semiconductor film on top of an insulating substance using the VHF-PECVD process or the microwave PECVD process and then crystallizing this film using solid phase crystallization, such as RTA or VST-SPC, or crystallizing it using melt crystallization, such as by laser irradiation, and then having the subsequent process steps take place at 350xc2x0 C. or lower.
Films deposited by VHF-PECVD or by microwave PECVD have quality closer to that of films deposited using LPCVD than to films deposited by PECVD. For this reason, the relationship between the transistor properties and semiconductor film thickness obtained when producing a thin film semiconductor device through crystallization becomes equivalent to the relationship possessed by a thin film semiconductor device produced by the LPCVD process. In contrast to semiconductor films produced by the LPCVD process, however, which show almost no reduction in film thickness before and after crystallization, some slight reduction can be found in VHF-PECVD and microwave PECVD films. Therefore, when crystallizing such films to produce thin film semiconductor devices, the discussion in section (2-6) can be applied as is by considering the semiconductor film thickness after crystallization to be the same as the film thickness of a film from the LPCVD-crystallization method.
As discussed in the foregoing, using this invention, high-quality semiconductor films comprised of polycrystalline silicon films and others can be easily formed at low temperatures of less than about 450xc2x0 C. and 430xc2x0 C. or lower. Thus, this invention greatly improves the properties of thin film semiconductor devices as well as brings about reliable mass production. To be specific, it has the effects that are described below.
Effect 1). Since the processing temperatures are below about 450xc2x0 C., low-cost glass can be used and it is possible to lower the price of the products. Additionally, since it is possible to prevent the warpage of the glass under its own weight, it is easily possible to increase the size of liquid crystal displays (LCDs).
Effect 2). Since the processing temperatures are approximately 350xc2x0 C. or less, there is no thermal degradation of the underlevel insulator layer or gate insulator layer; and it is possible to easily produce high-performance thin film semiconductor devices with excellent reliability.
Effect 3). Laser irradiation can be applied uniformly over the entire substrate. The result of this is that the uniformity of each lot is improved, and reliable production has become possible.
Effect 4). The formation of self-aligned TFTs in which the gate electrode is aligned with the source and drain by ion doping and subsequent low temperature activation at approximately 300xc2x0 C.xcx9c350xc2x0 C. has become remarkably easy. As a result, it has become possible to reliably activate impurity ions. Additionally, it has become possible to easily and reliably fabricate lightly doped drain (LDD) TFTs. Because LDD TFTs have been realized by low temperature process poly-Si TFTs, it has become possible to decrease TFT element size and off leak currents.
Effect 5). In the prior art, only low temperature poly-Si TFTs having SiO2 made by ECR-PECVD showed good transistor characteristics. Using this invention, however, this has become possible using conventional PECVD reactors. Consequently, practical gate insulator layer fabrication equipment applicable to large substrates and suitable for mass production has been achieved.
Effect 6). Thin film semiconductor devices with higher on currents and lower off currents than those produced by the prior art have been obtained. Additionally, the non-uniformity in these values has been decreased.
Effect 7). When using low price, conventional glass, it has become possible to form underlevel protection layers which effectively prevent the incorporation of impurities from the substrate into the semiconductor film and simultaneously act as the underlevel protection layer for thin film semiconductor devices showing optimum electrical properties. Also, the degradation of the electrical properties of thin film semiconductor devices as a result of stress from the underlevel protection layer and the generation of cracks in the thin film semiconductor devices have been avoided.
Effect 8). The incorporation of constitutive elements such as fluorine (F) and carbon (C) from cleaning vapors into the semiconductor films when such films are formed by plasma enhanced chemical vapor deposition (PECVD) has been prevented. As a result, the amount of impurities among substrates can always be kept to a minimum and it has become possible to reliably fabricate excellent thin film semiconductor devices.
Effect 9). Even when depositing semiconductor films by low pressure chemical vapor deposition (LPCVD) at low temperatures less than about 450xc2x0 C., it has become possible to simultaneously achieve uniformity, both within a single substrate and among different substrates, and a suitable deposition rate. Therefore, it is possible to accommodate increasing substrate size; and it has become possible to mass produce large-area LCDs.
Effect 10). Three types of variation in electrical properties of thin film semiconductor devices are recognized: variation within a single substrate, variation among substrates within the same lot, and variation from lot to lot. Using this invention, however, all three types of variation can be controlled. The variation among lots processed by PECVD has been particularly significantly improved.
Effect 11). Even when the semiconductor film is grown by PECVD, good adhesion between the semiconductor film and the underlevel protection layer can be achieved. In other words, problems such as the generation of numerous crater-shaped holes in the semiconductor film and peeling of the films have been avoided.
Effect 12). Even without special crystallization processing, poly-Si TFTs can be fabricated reliably on large-area substrates by low temperature processing less than or equal to about 350xc2x0 C.